coreboot-gerrit October 2023

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[S] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Add SCP domain setting
by Yu-Ping Wu (Code Review) 02 Oct '23

02 Oct '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77883?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: devapc: Add SCP domain setting ...................................................................... soc/mediatek/mt8188: devapc: Add SCP domain setting Configure the SCP to operate within domain 8, allowing it to access only the necessary registers. Any unauthorized access will be prevented by the DAPC. - Set SCP domain from domain 0 to domain 8. - Lock register settings down to prevent unexpected modification. BUG=b:270657858 TEST=scp bootup successful with dapc settings Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/addressmap.h M src/soc/mediatek/mt8188/include/soc/devapc.h 3 files changed, 39 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, but someone else must approve build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index b30856f..03e0dfd 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1628,6 +1628,15 @@ base, read32(getreg(base, DOM_REMAP_0_0))); } +static void dump_scp_master(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] SCP_DOM0:%#x SCP_DOM1:%#x SCP_DOM2:%#x Lock:%#x\n", + read32(getreg(base, SCP_DOM0)), + read32(getreg(base, SCP_DOM1)), + read32(getreg(base, SCP_DOM2)), + read32(getreg(base, ONETIME_LOCK))); +} + static void infra_init(uintptr_t base) { void *reg; @@ -1745,6 +1754,27 @@ FOUR_BIT_DOM_REMAP_7, DOMAIN_15); } +static void scp_master_init(uintptr_t base) +{ + SET32_BITFIELDS(getreg(base, SCP_DOM0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_8, + FOUR_BIT_DOM_REMAP_2, DOMAIN_8, + FOUR_BIT_DOM_REMAP_4, DOMAIN_8, + FOUR_BIT_DOM_REMAP_6, DOMAIN_8); + + SET32_BITFIELDS(getreg(base, SCP_DOM1), + FOUR_BIT_DOM_REMAP_0, DOMAIN_8, + FOUR_BIT_DOM_REMAP_2, DOMAIN_8, + FOUR_BIT_DOM_REMAP_4, DOMAIN_8, + FOUR_BIT_DOM_REMAP_6, DOMAIN_8); + + SET32_BITFIELDS(getreg(base, SCP_DOM2), + FOUR_BIT_DOM_REMAP_0, DOMAIN_8); + + /* Let SCP_DOM registers be read-only for security */ + write32(getreg(base, ONETIME_LOCK), 0x5); +} + const struct devapc_init_ops devapc_init[] = { { DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc }, { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, @@ -1752,6 +1782,7 @@ { DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc }, { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, { DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao }, + { SCP_CFG_BASE, scp_master_init, dump_scp_master }, }; const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init); diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index 01620b4..53e5214 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -58,6 +58,7 @@ INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, + SCP_CFG_BASE = IO_PHYS + 0x00700000, SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index 177cd3c..d71377c 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -19,6 +19,13 @@ AO_APC_CON = 0x00F00, }; +enum scp_offset { + SCP_DOM0 = 0xA0900, + SCP_DOM1 = 0xA0904, + SCP_DOM2 = 0xA0908, + ONETIME_LOCK = 0xA5104, +}; + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ -- To view, visit https://review.coreboot.org/c/coreboot/+/77883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Gerrit-Change-Number: 77883 Gerrit-PatchSet: 8 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Set master domains
by Yu-Ping Wu (Code Review) 02 Oct '23

02 Oct '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77862?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: devapc: Set master domains ...................................................................... soc/mediatek/mt8188: devapc: Set master domains Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch sets domains for masters: SSPM - domain 3 CPUEB - domain 14 PCIE0 - domain 2 SPM - domain 9 Change-Id: Ie3e1d5055e72824257b66d6257982652eeb05953 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77862 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/devapc.h 2 files changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 72ba222..b30856f 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1636,6 +1636,11 @@ SET32_BITFIELDS(getreg(base, MAS_SEC_0), CPU_EB_SEC, SECURE_TRANS); SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), + SCP_SSPM_DOM, DOMAIN_3, + CPU_EB_DOM, DOMAIN_14); + /* * Domain Remap: INFRA (4-bit) -> MMSYS (2-bit) * domain 0 -> domain 0 @@ -1670,6 +1675,9 @@ /* Default APC setting */ set_peri_ao_apc(base); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, DOMAIN_9); + /* * Domain Remap: INFRA (4-bit) -> TINYSYS (3-bit) * domain 0 -> domain 0 @@ -1694,6 +1702,11 @@ { /* Default APC setting */ set_peri_par_ao_apc(base); + + /* Master Domain */ + SET32_BITFIELDS(getreg_domain(base, MAS_DOM_0, 0, 4), + PCIE0_DOM, DOMAIN_2); + } static void fmem_master_init(uintptr_t base) diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index 0f320ba..177cd3c 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -59,4 +59,13 @@ DEFINE_BIT(CPU_EB_SEC, 1) DEFINE_BIT(SCP_SSPM_SEC, 2) +DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 1 */ +DEFINE_BITFIELD(SCP_SSPM_DOM, 19, 16) /* 2 */ + +/* PERI */ +DEFINE_BITFIELD(SPM_DOM, 3, 0) /* 0 */ + +/* PERI_PAR */ +DEFINE_BITFIELD(PCIE0_DOM, 27, 24) /* 19 */ + #endif /* SOC_MEDIATEK_MT8188_DEVAPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/77862?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3e1d5055e72824257b66d6257982652eeb05953 Gerrit-Change-Number: 77862 Gerrit-PatchSet: 8 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Update permission for master domain setup
by Yu-Ping Wu (Code Review) 02 Oct '23

02 Oct '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77861?usp=email ) Change subject: soc/mediatek/mt8188: devapc: Update permission for master domain setup ...................................................................... soc/mediatek/mt8188: devapc: Update permission for master domain setup Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch updates the permission settings for domains 2, 3, 4, 5, 7, 8, 9, and 14, as these domains will be assigned masters in the upcoming patch. BUG=b:270657858 TEST=build pass Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77861 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/addressmap.h M src/soc/mediatek/mt8188/include/soc/devapc.h 3 files changed, 284 insertions(+), 119 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 5890a8e..72ba222 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -6,32 +6,38 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION2, FORBIDDEN3, + NO_PROTECTION2, FORBIDDEN4, NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("TINSYS_AO_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION2, FORBIDDEN3, + NO_PROTECTION2, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN4, NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), /* 10 */ DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S", @@ -39,18 +45,19 @@ DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), /* 20 */ DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S", @@ -62,7 +69,8 @@ DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S", @@ -71,9 +79,9 @@ DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S", @@ -96,11 +104,11 @@ DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S", SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("SRCLKEN_RC_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1", @@ -125,24 +133,30 @@ DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, SEC_RW_ONLY, FORBIDDEN4, + SEC_RW_ONLY, FORBIDDEN7), DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4", NO_PROTECTION, FORBIDDEN15), /* 60 */ DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, SEC_RW_ONLY, FORBIDDEN4, + SEC_RW_ONLY, FORBIDDEN7), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("L3C_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1", @@ -150,7 +164,7 @@ DAPC_INFRA_AO_SYS0_ATTR("L3C_S-2", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 70 */ DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S", NO_PROTECTION, FORBIDDEN15), @@ -167,28 +181,28 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), /* 10 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12", @@ -202,7 +216,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19", @@ -324,7 +338,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-74", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-75", - NO_PROTECTION, FORBIDDEN3), + SEC_RW_ONLY, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-76", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-77", @@ -427,7 +441,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-1", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-2", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-3", @@ -450,7 +464,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-11", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-12", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-13", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-14", @@ -484,7 +498,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-27", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-28", - NO_PROTECTION, FORBIDDEN3), + SEC_RW_ONLY, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-29", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-30", @@ -524,9 +538,9 @@ NO_PROTECTION, FORBIDDEN3), /* 170 */ DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-47", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-48", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-49", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-50", @@ -580,9 +594,9 @@ DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-73", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-74", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-75", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION2, FORBIDDEN2), DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-76", NO_PROTECTION, FORBIDDEN3), /* 200 */ @@ -913,97 +927,141 @@ DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), /* 10 */ DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), /* 20 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), /* 30 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), /* 40 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S", @@ -1022,9 +1080,11 @@ DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S", SEC_RW_ONLY, FORBIDDEN15), }; @@ -1046,7 +1106,7 @@ DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S", @@ -1103,7 +1163,7 @@ DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB1_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB2_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB3_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB4_S", @@ -1195,7 +1255,8 @@ DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION2, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S", @@ -1206,7 +1267,7 @@ NO_PROTECTION, FORBIDDEN15), /* 80 */ DAPC_PERI2_AO_SYS0_ATTR("SRAMROM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("ECC_TOP_APB_S", @@ -1222,18 +1283,19 @@ DAPC_PERI2_AO_SYS0_ATTR("DEBUG_TRACKER_APB1_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB0_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB1_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), /* 90 */ DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB2_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB3_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S", SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S", @@ -1262,7 +1324,8 @@ DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S", SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_SUB_INFRA_APB_S", @@ -1271,7 +1334,8 @@ DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S", @@ -1279,11 +1343,13 @@ DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB1_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN7), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6), DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MDP_S", @@ -1323,7 +1389,7 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P3_S", @@ -1331,7 +1397,8 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN), DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S", @@ -1346,7 +1413,8 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S", @@ -1384,9 +1452,10 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PERICFG2_AO_APB_S", @@ -1547,10 +1616,48 @@ read32(getreg(base, MAS_SEC_0))); } +static void dump_fmem_ao(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_infra2_ao(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA2_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + static void infra_init(uintptr_t base) { + void *reg; + /* Side-band */ - SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS); + SET32_BITFIELDS(getreg(base, MAS_SEC_0), CPU_EB_SEC, SECURE_TRANS); + SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS); + + /* + * Domain Remap: INFRA (4-bit) -> MMSYS (2-bit) + * domain 0 -> domain 0 + * domain 8 -> domain 1 (SCP) + * others -> domain 3 + */ + reg = getreg(base, DOM_REMAP_2_0); + write32(reg, 0xFFFFFFFF); + SET32_BITFIELDS(reg, + TWO_BIT_DOM_REMAP_0, DOMAIN_0, + TWO_BIT_DOM_REMAP_8, DOMAIN_1); + + /* + * Domain Remap: TINYSYS (3-bit) -> INFRA (4-bit) + * domain 0 -> domain 4 (DSP) + * others -> domain 15 + */ + reg = getreg(base, DOM_REMAP_0_0); + write32(reg, 0xFFFFFFFF); + SET32_BITFIELDS(reg, + FOUR_BIT_DOM_REMAP_0, DOMAIN_4); + /* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */ set_infra_ao_apc(base); @@ -1558,8 +1665,23 @@ static void peri_init(uintptr_t base) { + void *reg; + /* Default APC setting */ set_peri_ao_apc(base); + + /* + * Domain Remap: INFRA (4-bit) -> TINYSYS (3-bit) + * domain 0 -> domain 0 + * domain 4 -> domain 0 (DSP) + * others -> domain 7 + */ + reg = getreg(base, DOM_REMAP_0_0); + write32(reg, 0xFFFFFFFF); + SET32_BITFIELDS(reg, + THREE_BIT_DOM_REMAP_0, DOMAIN_0, + THREE_BIT_DOM_REMAP_4, DOMAIN_0); + write32(getreg(base, DOM_REMAP_0_1), 0xFFFFFFFF); } static void peri2_init(uintptr_t base) @@ -1574,11 +1696,49 @@ set_peri_par_ao_apc(base); } +static void fmem_master_init(uintptr_t base) +{ + /* + * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. DSP from 0 to 4 + * 2. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_4, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_15, + FOUR_BIT_DOM_REMAP_4, DOMAIN_15, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void infra2_master_init(uintptr_t base) +{ + /* + * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. DSP from 0 to 4 + * 2. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_4, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_15, + FOUR_BIT_DOM_REMAP_4, DOMAIN_15, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + const struct devapc_init_ops devapc_init[] = { { DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc }, { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, { DEVAPC_PERI2_AO_BASE, peri2_init, dump_peri2_ao_apc }, { DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc }, + { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, + { DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao }, }; const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init); diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index 7448976..01620b4 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -41,6 +41,7 @@ DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, PERI_PAR_AO_BASE = IO_PHYS + 0x00040000, FMEM_AO_BASE = IO_PHYS + 0x00042000, + DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, DBG_TRACKER_BASE = IO_PHYS + 0x00208000, PERI_TRACKER_BASE = IO_PHYS + 0x00218000, EMI0_BASE = IO_PHYS + 0x00219000, @@ -52,6 +53,7 @@ I2C4_DMA_BASE = IO_PHYS + 0x00220380, I2C5_DMA_BASE = IO_PHYS + 0x00220480, I2C6_DMA_BASE = IO_PHYS + 0x00220600, + DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index 161ae9b..0f320ba 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -11,13 +11,14 @@ SYS0_D0_APC_0 = 0x00000, SYS1_D0_APC_0 = 0x01000, SYS2_D0_APC_0 = 0x02000, + DOM_REMAP_0_0 = 0x00800, + DOM_REMAP_0_1 = 0x00804, + DOM_REMAP_2_0 = 0x00820, MAS_DOM_0 = 0x00900, MAS_SEC_0 = 0x00A00, AO_APC_CON = 0x00F00, }; -DEFINE_BIT(MCUPM_SEC, 1) - /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ @@ -54,6 +55,8 @@ /****************************************************************************** * Bit Field DEFINITION ******************************************************************************/ - /* TODO */ +/* INFRA */ +DEFINE_BIT(CPU_EB_SEC, 1) +DEFINE_BIT(SCP_SSPM_SEC, 2) #endif /* SOC_MEDIATEK_MT8188_DEVAPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/77861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Gerrit-Change-Number: 77861 Gerrit-PatchSet: 8 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Update permission for master domain setup
by Yu-Ping Wu (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77861?usp=email ) Change subject: soc/mediatek/mt8188: devapc: Update permission for master domain setup ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Gerrit-Change-Number: 77861 Gerrit-PatchSet: 7 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 06:31:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs
by Subrata Banik (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Arthur Heymans, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Paul Menzel, Tarun, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78079?usp=email ) Change subject: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78079/comment/317f911f_00c4fcd4 : PS2, Line 18: > I always wonder, why this can’t be detected at run-time by some PCI(?) (chipset) ID or so. Then no Kconfig option would be needed. Code size does not matter in this case, I think. There is no such chipset ID to tell GMA v1 or v2 for say. Also if you are interested to know what this Kconfig is guarding, then its register definition which is meant to be an uprev over the previous generation chipsets (starting with TGL) https://review.coreboot.org/c/coreboot/+/78078/2/src/drivers/intel/gma/i915… -- To view, visit https://review.coreboot.org/c/coreboot/+/78079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Gerrit-Change-Number: 78079 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 06:28:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb: Enable VBOOT_LID_SWITCH by default
by Karthik Ramasubramanian (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Alexander Couzens, Christian Walter, Eran Mitrani, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jason Nien, Julius Werner, Kapil Porwal, Martin Roth, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Werner Zeh, Yidi Lin, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78207?usp=email ) Change subject: mb: Enable VBOOT_LID_SWITCH by default ...................................................................... Patch Set 3: (1 comment) File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/78207/comment/e19dea85_ffb68c0f : PS3, Line 179: default y Enabling it only when EC_GOOGLE_CHROMEEC_SWITCHES is enabled and keeping it disabled for others will limit the scope of this change to just Google Mainboards -- To view, visit https://review.coreboot.org/c/coreboot/+/78207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I922c04e0fa0675090cea7c7b3f4e2275eb70f523 Gerrit-Change-Number: 78207 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 05:41:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: {lib, ec/google}: Add weak implementation for get_lid_switch()
by Karthik Ramasubramanian (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jakub Czapiga, Julius Werner, Nick Vaccaro, Nick Vaccaro, Subrata Banik, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78076?usp=email ) Change subject: {lib, ec/google}: Add weak implementation for get_lid_switch() ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/switches.c: https://review.coreboot.org/c/coreboot/+/78076/comment/40b3c933_5f06eb0e : PS1, Line 9: if (!CONFIG(VBOOT_LID_SWITCH)) > > > Oh, right because Chromeboxes still have ECs. Okay that makes sense. […] Verified Boot is used in non-ChromeOS boards too. Having said that, updating CB:78207 as below(something along that line) will limit the scope to Google main boards alone. That way you need to disable VBOOT_LID_SWITCH only for Chromeboxes and Chromebases. ``` config VBOOT_LID_SWITCH bool default y if EC_GOOGLE_CHROMEEC_SWITCHES default n <snip> ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8847bc6f08f5d9cecf9d9ddaf33c44bd40491e98 Gerrit-Change-Number: 78076 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 05:37:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Update permission for master domain setup
by Paul Menzel (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, jason-ch chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77861?usp=email ) Change subject: soc/mediatek/mt8188: devapc: Update permission for master domain setup ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Gerrit-Change-Number: 77861 Gerrit-PatchSet: 7 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 05:36:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb: Enable VBOOT_LID_SWITCH by default
by Paul Menzel (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Alexander Couzens, Christian Walter, Eran Mitrani, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jason Nien, Julius Werner, Kapil Porwal, Martin Roth, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Stefan Ott, Subrata Banik, Tarun, Werner Zeh, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78207?usp=email ) Change subject: mb: Enable VBOOT_LID_SWITCH by default ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78207/comment/79236b1f_eae9bd8e : PS3, Line 16: Chromeosbox I think the official name is Chromebox. -- To view, visit https://review.coreboot.org/c/coreboot/+/78207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I922c04e0fa0675090cea7c7b3f4e2275eb70f523 Gerrit-Change-Number: 78207 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 05:34:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs
by Paul Menzel (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Arthur Heymans, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78079?usp=email ) Change subject: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78079/comment/3242b187_7c3245cf : PS2, Line 7: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs Please make it a statement by adding a verb (in imperative mood). Maybe: > Select … https://review.coreboot.org/c/coreboot/+/78079/comment/4d4a8dcf_17d60148 : PS2, Line 18: I always wonder, why this can’t be detected at run-time by some PCI(?) (chipset) ID or so. Then no Kconfig option would be needed. Code size does not matter in this case, I think. -- To view, visit https://review.coreboot.org/c/coreboot/+/78079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Gerrit-Change-Number: 78079 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 05:33:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2023