coreboot-gerrit October 2023

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[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Patrick Rudolph (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Patrick Rudolph. Hello Felix Held, Krystian Hebel, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78192?usp=email to look at the new patch set (#2). Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... x86/include/arch/cpuid.h: Fix inline assembly In the cpuid helper functions eax is always written to by the cpuid instruction, so add it to the output clobbered list. This prevents GCC from generating code with undefined behaviour when the function is inlined. Test: Verified that the generated assembly is sane and runtime tests showed no "strange" behaviour when calling cpuid functions. Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/cpuid.h 1 file changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/78192/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: configs: Fix FSP binaries for config.google.skyrim.with_binaries
by Paul Menzel (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Matt DeVillier. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78195?usp=email ) Change subject: configs: Fix FSP binaries for config.google.skyrim.with_binaries ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Gerrit-Change-Number: 78195 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Oct 2023 03:59:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Latest test results
by Paul Menzel (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78204?usp=email ) Change subject: Documentation/mb/asus/p8z77-m: Latest test results ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78204/comment/37141411_15c6017c : PS1, Line 7: Documentation/mb/asus/p8z77-m: Latest test results Maybe: > Add/Document latest test results File Documentation/mainboard/asus/p8z77-m.md: https://review.coreboot.org/c/coreboot/+/78204/comment/bb8673fe_00073ff6 : PS1, Line 61: edk2 Please add the version. -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Oct 2023 03:58:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Fix ACPI S3 suspend
by Paul Menzel (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Keith Hui. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78205?usp=email ) Change subject: mb/asus/p8z77-m: Fix ACPI S3 suspend ...................................................................... Patch Set 1: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78205/comment/1d2654c9_fecdc8ee : PS1, Line 7: Fix ACPI S3 suspend Maybe: > Enable 3VSBSW# to fix ACPI S3 suspend https://review.coreboot.org/c/coreboot/+/78205/comment/cb435d56_b7d5e483 : PS1, Line 11: Maybe mention Super I/O name, and 3VSBSW# in her. https://review.coreboot.org/c/coreboot/+/78205/comment/cca2a67f_45a253be : PS1, Line 16: Maybe add a Fixes: tag with the commit regressing your board. Patchset: PS1: Nice work. -- To view, visit https://review.coreboot.org/c/coreboot/+/78205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Gerrit-Change-Number: 78205 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Oct 2023 03:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Only use supported C-states
by Paul Menzel (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78194?usp=email ) Change subject: cpu/intel/model_206ax: Only use supported C-states ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78194/comment/d82b33b1_aba5ee05 : PS1, Line 9: Make sure that the C-state is supported by the CPU. : Downgrade if it's not and make sure to not advertise : duplicate states. Would be less lines, if you used 72 characters per line. File src/cpu/intel/model_206ax/acpi.c: https://review.coreboot.org/c/coreboot/+/78194/comment/3c88baea_6cd9b38f : PS1, Line 110: BIOS_DEBUG Should this be info? -- To view, visit https://review.coreboot.org/c/coreboot/+/78194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Gerrit-Change-Number: 78194 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sun, 01 Oct 2023 03:56:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Use haswell cstate_map
by Paul Menzel (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78193?usp=email ) Change subject: cpu/intel/model_206ax: Use haswell cstate_map ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Gerrit-Change-Number: 78193 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sun, 01 Oct 2023 03:55:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Paul Menzel (Code Review) 01 Oct '23

01 Oct '23

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78192/comment/88fce5bb_bd1491c7 : PS1, Line 12: prevent prevents -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sun, 01 Oct 2023 03:51:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data
by Keith Hui (Code Review) 01 Oct '23

01 Oct '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78206?usp=email ) Change subject: [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data ...................................................................... [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data Portions of MRC raminit code only serves to enter fixed constants into pei_data structure for MRC consumption. Since the constants are concentrated in the front of the structure, set up a truncated copy for compiler to render at build time. Chipset code then uses it as a base to initialize the (in-CAR) structure and fill in the remainder at runtime. This trades 58 bytes of static data for 111 bytes of executable code, for a presumed net saving of 53 bytes, yet romstage gained no actual savings. This is therefore submitted as an RFC. Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 40 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78206/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 69baf44..ee9e0e9 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -230,16 +230,47 @@ u32 reserved[4]; } __packed; +/* This is a simple truncation of pei_data struct. + All members must match up to the cut. */ +struct pei_data_truncated +{ + uint32_t pei_version; + uint32_t mchbar; + uint32_t dmibar; + uint32_t epbar; + uint32_t pciexbar; + uint16_t smbusbar; + uint32_t wdbbar; + uint32_t wdbsize; + uint32_t hpet_address; + uint32_t rcba; + uint32_t pmbase; + uint32_t gpiobase; + uint32_t thermalbase; + uint32_t system_type; + uint32_t tseg_size; +} __packed; + +const struct pei_data_truncated pd = { + .pei_version = PEI_VERSION, + .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, + .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, + .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_BASE_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .tseg_size = CONFIG_SMM_TSEG_SIZE, +}; + static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE; - pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; - pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; - pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS; - pei_data->hpet_address = HPET_BASE_ADDRESS; - pei_data->thermalbase = 0xfed08000; pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); - pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { const struct device *dev = pcidev_on_root(1, 0); @@ -253,12 +284,6 @@ { const struct device *dev = pcidev_on_root(0x19, 0); - pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; - pei_data->wdbbar = 0x04000000; - pei_data->wdbsize = 0x1000; - pei_data->rcba = (uintptr_t)DEFAULT_RCBA; - pei_data->pmbase = DEFAULT_PMBASE; - pei_data->gpiobase = DEFAULT_GPIOBASE; pei_data->gbe_enable = dev && dev->enabled; } @@ -332,7 +357,8 @@ enable_usb_bar(); memset(&pei_data, 0, sizeof(pei_data)); - pei_data.pei_version = PEI_VERSION; + /* Initialize with pre-rendered values from a shortened copy */ + memcpy(&pei_data, &pd, sizeof(pd)); northbridge_fill_pei_data(&pei_data); southbridge_fill_pei_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/78206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f Gerrit-Change-Number: 78206 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2023