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Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
now its can pick in mainline?
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Change subject: soc/amd: rework SPL file override and SPL fusing handling
......................................................................
Patch Set 2: Code-Review+2
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Hello Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: rework SPL file override and SPL fusing handling
......................................................................
soc/amd: rework SPL file override and SPL fusing handling
The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a
way to override the default SPL file configured in the SoC's fw.cfg file
by passing the '--spl-table' parameter to amdfwtool which will then use
the override instead of the SPL file from the fw.cfg file. When
SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix
call in the makefile will result in no '--spl-table' parameter being
passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In
order to not pass an SPL override by default, remove the default from
the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the
same SPL file as in fw.cfg file anyway. Now only when a mainboard sets
this option to point to a file, that file will be used as an override.
This override is used to include a special SPL file needed for the
verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an
empty string by default, neither the SPL_TABLE_FILE Kconfig option nor
it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE,
so remove the dependency in the Kconfig and the ifeq in the Makefile.
Before this patch, the HAVE_SPL_FILE option controlled two things that
shouldn't be controlled by the same Kconfig option: Only when
HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into
account, and it also controls if spl_fuse.c got added to the build which
when added will send the SPL fusing command to the PSP. So the case of
needing an SPL file override, but not updating the SPL fuses wasn't
supported before.
The SPL file in the amdfw part will be used by the PSP bootloader for
the anti-rollback feature which makes sure that the SPL file version
isn't lower than what is in the SPL fuses. For this the SPL file needs
to be present in the PSP directory table. The SPL version check happens
way before we're running code on the x86 cores. The SPL fusing PSP
command that can be sent by coreboot will tell the PSP to update the SPL
fuses so that the fused minimal SPL version will be updated to the
current SPL version.
Since the former HAVE_SPL_FILE option now only controls if the SPL
fusing command will be sent to the PSP mailbox, rename it to
PERFORM_SPL_FUSING to clarify what this will do and update the help text
correctly describe what this does.
TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman
with Phoenix APU and Skyrim result in identical binaries.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/skyrim/Kconfig
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/common/block/psp/Makefile.inc
M src/soc/amd/genoa/Kconfig
M src/soc/amd/genoa/Makefile.inc
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/Makefile.inc
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/Makefile.inc
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/Makefile.inc
13 files changed, 88 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/78178/2
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Change subject: soc/intel/alderlake: Hook up FSP repo for RPL-P/S
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake: Hook up FSP repo for RPL-P/S
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/78190/comment/505162b3_5b5b9d30 :
PS1, Line 427: default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
> completely agree, but figured that should be a separate patch (along with dropping the now-superfluo […]
Acknowledged
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Change subject: soc/intel/alderlake: Hook up FSP repo for RPL-P/S
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/78190/comment/ffac0c34_554c33ed :
PS1, Line 427: default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
> Actually, this should not be needed anymore if RPL-S FSP is here. We could basically drop ADL-S FSP.
completely agree, but figured that should be a separate patch (along with dropping the now-superfluous vendorcode headers). I wanted this patch to simply add support for using the RPL-U/P binaries/headers in the submodule without changing the behavior for any existing boards/configs.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78176?usp=email )
Change subject: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits
......................................................................
soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits
Simplify the code a bit by returning 0 early in the function when the
SYSCFG_MSR_SMEE bit isn't set.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Suggested-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78176
Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/cpu/noncar/cpu.c
1 file changed, 4 insertions(+), 5 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jérémy Compostella: Looks good to me, but someone else must approve
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index eefd62f..136cb42 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -38,10 +38,9 @@
/* Number of most significant physical address bits reserved for secure memory encryption */
unsigned int get_reserved_phys_addr_bits(void)
{
- if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE)
- return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) &
- CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >>
- CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT;
- else
+ if (!(rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE))
return 0;
+
+ return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >>
+ CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT;
}
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78074?usp=email )
Change subject: soc/amd/common: use common physical address bit reservation code
......................................................................
soc/amd/common: use common physical address bit reservation code
Instead of having the get_usable_physical_address_bits function that
only got used in the data fabric domain resource reporting code, drop
this function, select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT in the
common AMD non-CAR CPU and rename get_sme_reserved_address_bits to
get_reserved_phys_addr_bits so that the common cpu_phys_address_size
function will return the correct number of usable physical address bits
which now can be used everywhere. The common AMD CAR CPU support is only
selected by Stoneyridge which doesn't support secure memory encryption,
so RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT isn't selected by the
SOC_AMD_COMMON_BLOCK_CAR Kconfig option.
Before only the MMIO region reporting took the reserved physical address
bits into account, but now also the MTRR calculation will take those
reserved bits into account. See the AMD64 Programmers Manual volume 2
(document number 24593) for details. Chapter 7.10.5 from revision 3.41
of this document was used as a reference. The MTRR handling code in
older Linux kernels complains when the upper reserved bits in the MTRR
mask weren't set, but sets them after complaining and then continues to
boot. This issue is no longer present in version 6.5 of the Linux
kernel.
The calculation of the TSEG mask however still needs to take all
physical bits into account, including the ones reserved for the memory
encryption. When not setting the reserved bits in the TSEG mask, the
Mandolin board with a Picasso APU won't boot to the OS any more due to
not returning from SeaBIOS calling into the VBIOS. Haven't root-caused
what exactly causes this breakage, but I think previously when something
else was wrong with the SMM initialization, also something went wrong
when calling into the VBIOS.
TEST=Ubuntu 2023.10 nightly build boots on Mandolin via SeaBIOS and EDK2
and Windows 10 boots on it via EDK2.
TEST=On Ubuntu 2022.04 LTS, the kernel complained with the following
warning, but it still continues the boot process as described above:
mtrr: your BIOS has configured an incorrect mask, fixing it.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78074
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/cpu/Kconfig
M src/soc/amd/common/block/cpu/noncar/Makefile.inc
M src/soc/amd/common/block/cpu/noncar/cpu.c
M src/soc/amd/common/block/cpu/smm/smm_relocate.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/include/amdblocks/cpu.h
6 files changed, 12 insertions(+), 10 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 6c5329a..f926887 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -13,6 +13,7 @@
config SOC_AMD_COMMON_BLOCK_NONCAR
bool
+ select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT
help
From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
more, since the RAM initialization is already done by the PSP when
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index 3204667..f8ca357 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -2,6 +2,7 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
bootblock-y += bootblock.c
+bootblock-y += cpu.c
bootblock-y += early_cache.c
bootblock-y += pre_c.S
bootblock-y += write_resume_eip.c
diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index eec593c..eefd62f 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -35,7 +35,8 @@
wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
}
-static uint32_t get_sme_reserved_address_bits(void)
+/* Number of most significant physical address bits reserved for secure memory encryption */
+unsigned int get_reserved_phys_addr_bits(void)
{
if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE)
return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) &
@@ -44,8 +45,3 @@
else
return 0;
}
-
-uint32_t get_usable_physical_address_bits(void)
-{
- return cpu_phys_address_size() - get_sme_reserved_address_bits();
-}
diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
index 4004726..ae00885 100644
--- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c
+++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
@@ -65,6 +65,11 @@
uintptr_t tseg_base;
size_t tseg_size;
+ /* For the TSEG masks all physical address bits including the ones reserved for memory
+ encryption need to be taken into account. TODO: Find out why this is the case */
+ const unsigned int total_physical_address_bits =
+ cpu_phys_address_size() + get_reserved_phys_addr_bits();
+
smm_region(&tseg_base, &tseg_size);
msr_t msr;
@@ -73,7 +78,7 @@
msr.lo = ~(tseg_size - 1);
msr.lo |= SMM_TSEG_WB;
- msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
+ msr.hi = (1 << (total_physical_address_bits - 32)) - 1;
wrmsr(SMM_MASK_MSR, msr);
uintptr_t smbase = smm_get_cpu_smbase(cpu_index());
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index ca685b2..01fad99 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -1,13 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
-#include <amdblocks/cpu.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
#include <arch/vga.h>
#include <console/console.h>
#include <cpu/amd/mtrr.h>
+#include <cpu/cpu.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <types.h>
@@ -90,7 +90,7 @@
/* The last 12GB of the usable address space are reserved and can't be used for MMIO */
const resource_t reserved_upper_mmio_base =
- (1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE;
+ (1ULL << cpu_phys_address_size()) - DF_RESERVED_TOP_12GB_MMIO_SIZE;
for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 10dd23f..4aa225b 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -12,7 +12,6 @@
int get_cpu_count(void);
unsigned int get_threads_per_core(void);
void set_cstate_io_addr(void);
-uint32_t get_usable_physical_address_bits(void);
void write_resume_eip(void);
union pstate_msr; /* proper definition is in soc/msr.h */
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e
Gerrit-Change-Number: 78074
Gerrit-PatchSet: 6
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
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