coreboot-gerrit October 2023

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[S] Change in coreboot[main]: soc/amd/genoa: add GPIO support
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78222?usp=email ) Change subject: soc/amd/genoa: add GPIO support ...................................................................... soc/amd/genoa: add GPIO support Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/gpio.c 3 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/78222/1 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 328e7a2..3ec0db2 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -10,6 +10,7 @@ select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_LPC diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 2f7241d..a35146c 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -4,6 +4,7 @@ all-y += mmap_boot.c all-y += reset.c all-y += config.c +all-y += gpio.c bootblock-y += early_fch.c bootblock-y += aoac.c diff --git a/src/soc/amd/genoa/gpio.c b/src/soc/amd/genoa/gpio.c new file mode 100644 index 0000000..e8887ac --- /dev/null +++ b/src/soc/amd/genoa/gpio.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/gpio.h> +#include <soc/gpio.h> +#include <types.h> + +/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */ +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_7, GEVENT_11 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_21, GEVENT_5 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_14 }, + { GPIO_26, GEVENT_15 }, + { GPIO_76, GEVENT_11 }, + { GPIO_86, GEVENT_9 }, + { GPIO_89, GEVENT_0 }, + { GPIO_104, GEVENT_20 }, + { GPIO_105, GEVENT_22 }, + { GPIO_106, GEVENT_23 }, + { GPIO_115, GEVENT_1 }, + { GPIO_116, GEVENT_6 }, + { GPIO_129, GEVENT_17 }, +}; + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Gerrit-Change-Number: 78222 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/genoa: Add SMI support
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78221?usp=email ) Change subject: soc/amd/genoa: Add SMI support ...................................................................... soc/amd/genoa: Add SMI support Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig A src/soc/amd/genoa/include/soc/smi.h 2 files changed, 185 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/78221/1 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 598b4b6..328e7a2 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -15,6 +15,7 @@ select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_USE_ESPI select X86_CUSTOM_BOOTMEDIA diff --git a/src/soc/amd/genoa/include/soc/smi.h b/src/soc/amd/genoa/include/soc/smi.h new file mode 100644 index 0000000..abd9455 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/smi.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_GENOA_SMI_H +#define AMD_GENOA_SMI_H + +#include <types.h> + +/* @Todo: Update the SMI details for Genoa */ + +#define SMI_GEVENTS 24 +#define SCIMAPS 59 /* 0..58 */ +#define SCI_GPES 32 +#define NUMBER_SMITYPES 160 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +/* SMI source and status */ +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_GENINT2_L 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_LPCPME 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_LPCPD 5 +#define SMITYPE_G_SPKR 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_LPC_SMI_L 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO7 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_USBOC2_L 14 +#define SMITYPE_G_USBOC3_L 15 +#define SMITYPE_G_AGPIO23 16 +#define SMITYPE_G_ESPI_RESET_L 17 +#define SMITYPE_G_FANIN0 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO40 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPIO9 22 +#define SMITYPE_G_AGPIO8 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_GENINT2_L) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_LPCPME) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_LPCPD) \ + | (1 << SMITYPE_G_SPKR) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO7) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_USBOC2_L) \ + | (1 << SMITYPE_G_USBOC3_L) \ + | (1 << SMITYPE_G_AGPIO23) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ + | (1 << SMITYPE_G_FANIN0) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO40) \ + | (1 << SMITYPE_G_PWR_BTN_L) \ + | (1 << SMITYPE_G_AGPIO9) \ + | (1 << SMITYPE_G_AGPIO8)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L2 32 +#define SMITYPE_PSP 33 +/* 34,35 Reserved */ +#define SMITYPE_ESPI_SCI_B 36 +#define SMITYPE_WLAN_WLAN_PME 37 +#define SMITYPE_WLAN_BT_PME 38 +#define SMITYPE_AZPME 39 +#define SMITYPE_USB_PD_I2C4 40 +#define SMITYPE_GPIO_CTL 41 +/* 42 Reserved */ +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +/* 59-63 Reserved */ +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +/* 67-71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +/* 145 Reserved */ +#define SMITYPE_ESPI_SMI 146 +/* 147 Reserved */ +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ + +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 + +#define SMI_MODE_MASK 0x03 + +#endif /* AMD_GENOA_SMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Gerrit-Change-Number: 78221 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/amd/genoa: add GPIO definitions
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78220?usp=email ) Change subject: soc/amd/genoa: add GPIO definitions ...................................................................... soc/amd/genoa: add GPIO definitions Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- A src/soc/amd/genoa/include/soc/gpio.h 1 file changed, 258 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/78220/1 diff --git a/src/soc/amd/genoa/include/soc/gpio.h b/src/soc/amd/genoa/include/soc/gpio.h new file mode 100644 index 0000000..723eb19 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/gpio.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_GPIO_H +#define AMD_GENOA_GPIO_H + +/* @Todo: Updated GPIO device name for Genoa */ +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include <soc/iomap.h> +#include <amdblocks/gpio.h> +#endif /* !__ACPI__ */ + +#include <amdblocks/gpio_defs.h> + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 267 + +/* Bank 0: GPIO_0 - GPIO_63 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_26 26 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_86 86 +#define GPIO_87 87 +#define GPIO_88 88 +#define GPIO_89 89 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_108 108 +#define GPIO_109 109 +#define GPIO_110 110 +#define GPIO_115 115 +#define GPIO_116 116 +#define GPIO_117 117 +#define GPIO_118 118 +#define GPIO_119 119 +#define GPIO_120 120 +#define GPIO_121 121 +#define GPIO_122 122 +#define GPIO_123 123 +#define GPIO_124 124 +#define GPIO_125 125 +#define GPIO_126 126 + +/* Bank 2: GPIO_128 - GPIO_191 */ +#define GPIO_129 129 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_133 133 +#define GPIO_134 134 +#define GPIO_135 135 +#define GPIO_136 136 +#define GPIO_137 137 +#define GPIO_138 138 +#define GPIO_139 139 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 +#define GPIO_149 149 +#define GPIO_150 150 +#define GPIO_151 151 +#define GPIO_152 152 + +/* remote GPIO bank: GPIO_256 - GPIO_271 */ +#define GPIO_256 256 +#define GPIO_257 257 +#define GPIO_258 258 +#define GPIO_259 259 +#define GPIO_260 260 +#define GPIO_261 261 +#define GPIO_264 264 +#define GPIO_265 265 +#define GPIO_266 266 + +/* IOMUX function names and values */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIO_PU1PD0 1 +#define GPIO_0_IOMUX_GPIO 2 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_SATA_ACT_L 1 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_DEVSLP0 1 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_DEVSLP1 1 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_12_IOMUX_PWRGD_OUT 0 +#define GPIO_12_IOMUX_GPIOxx 1 +#define GPIO_13_IOMUX_I2C4_SCL 0 +#define GPIO_13_IOMUX_CLK_48_24_0 1 +#define GPIO_13_IOMUX_GPIOxx 2 +#define GPIO_14_IOMUX_I2C4_SDA 0 +#define GPIO_14_IOMUX_S0A3 1 +#define GPIO_14_IOMUX_GPIOxx 2 +#define GPIO_16_IOMUX_USB_1O_OC_L 0 +#define GPIO_16_IOMUX_GPIOxx 1 +#define GPIO_17_IOMUX_USB11_OC_L 0 +#define GPIO_17_IOMUX_GPIOxx 1 +#define GPIO_19_IOMUX_I2C5_SCL 0 +#define GPIO_19_IOMUX_SMBUS1_SCL 1 +#define GPIO_19_IOMUX_GPIOxx 2 +#define GPIO_20_IOMUX_I2C5_SDA 0 +#define GPIO_20_IOMUX_SMBUS1_SDA 1 +#define GPIO_20_IOMUX_GPIOxx 2 +#define GPIO_21_IOMUX_GPIOxx 0 +#define GPIO_21_IOMUX_SD0_CMD 3 +#define GPIO_22_IOMUX_GPIOxx 0 +#define GPIO_23_IOMUX_ESPI_RST_OUT_L 0 +#define GPIO_23_IOMUX_GPIOxx 1 +#define GPIO_24_IOMUX_SMERR_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_ESPI_CLK2 0 +#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_75_IOMUX_ESPI_CLK1 0 +#define GPIO_75_IOMUX_GPIOxx 1 +#define GPIO_76_IOMUX_GPIOxx 0 +#define GPIO_76_IOMUX_SPI_TPM_CS_L 1 +#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0 +#define GPIO_87_IOMUX_GPIOxx 0 +#define GPIO_88_IOMUX_GPIOxx 0 +#define GPIO_89_IOMUX_GENINT_L 0 +#define GPIO_89_IOMUX_PM_INTR_L 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_104_IOMUX_GPIOxx 0 +#define GPIO_105_IOMUX_GPIOxx 0 +#define GPIO_106_IOMUX_GPIOxx 0 +#define GPIO_107_IOMUX_GPIOxx 0 +#define GPIO_108_IOMUX_ESPI0_ALERT_D1 0 +#define GPIO_108_IOMUX_GPIOxx 1 +#define GPIO_109_IOMUX_GPIOxx 0 +#define GPIO_109_IOMUX_SD0_CLK 2 +#define GPIO_110_IOMUX_ESPI1_ALERT_D1 0 +#define GPIO_110_IOMUX_GPIOxx 1 +#define GPIO_115_IOMUX_GPIOxx 0 +#define GPIO_115_IOMUX_CLK_REQ11_L 1 +#define GPIO_116_IOMUX_GPIOxx 0 +#define GPIO_116_IOMUX_CLK_REQ12_L 1 +#define GPIO_117_IOMUX_ESPI_CLK0 0 +#define GPIO_117_IOMUX_GPIOxx 1 +#define GPIO_118_IOMUX_SPI_CS0_L 0 +#define GPIO_118_IOMUX_GPIOxx 1 +#define GPIO_119_IOMUX_SPI_CS1_L 0 +#define GPIO_119_IOMUX_GPIOxx 1 +#define GPIO_120_IOMUX_ESPI0_DATA0 0 +#define GPIO_120_IOMUX_GPIOxx 1 +#define GPIO_121_IOMUX_ESPI0_DATA1 0 +#define GPIO_121_IOMUX_GPIOxx 1 +#define GPIO_122_IOMUX_ESPI0_DATA2 0 +#define GPIO_122_IOMUX_GPIOxx 1 +#define GPIO_123_IOMUX_ESPI0_DATA3 0 +#define GPIO_123_IOMUX_GPIOxx 1 +#define GPIO_124_IOMUX_ESPI_CS0_L 0 +#define GPIO_124_IOMUX_GPIOxx 1 +#define GPIO_125_IOMUX_ESPI_CS1_L 0 +#define GPIO_125_IOMUX_GPIOxx 1 +#define GPIO_126_IOMUX_ESPI_CS2_L 0 +#define GPIO_126_IOMUX_GPIOxx 1 +#define GPIO_129_IOMUX_ESPI_RSTIN_L 0 +#define GPIO_129_IOMUX_KBRST_L 1 +#define GPIO_129_IOMUX_GPIOxx 2 +#define GPIO_131_IOMUX_ESPI1_DATA0 0 +#define GPIO_131_IOMUX_GPIOxx 1 +#define GPIO_132_IOMUX_ESPI1_DATA1 0 +#define GPIO_132_IOMUX_GPIOxx 1 +#define GPIO_133_IOMUX_ESPI1_DATA2 0 +#define GPIO_133_IOMUX_GPIOxx 1 +#define GPIO_134_IOMUX_ESPI1_DATA3 0 +#define GPIO_134_IOMUX_GPIOxx 1 +#define GPIO_135_IOMUX_UART0_CTS_L 0 +#define GPIO_135_IOMUX_UART2_TXD 1 +#define GPIO_135_IOMUX_GPIOxx 2 +#define GPIO_136_IOMUX_UART0_RXD 0 +#define GPIO_136_IOMUX_GPIOxx 1 +#define GPIO_137_IOMUX_UART0_RTS_L 0 +#define GPIO_137_IOMUX_UART2_RXD 1 +#define GPIO_137_IOMUX_GPIOxx 2 +#define GPIO_138_IOMUX_UART0_TXD 0 +#define GPIO_138_IOMUX_GPIOxx 1 +#define GPIO_139_IOMUX_UART0_INTR 0 +#define GPIO_139_IOMUX_GPIOxx 1 +#define GPIO_141_IOMUX_UART1_RXD 0 +#define GPIO_141_IOMUX_GPIOxx 1 +#define GPIO_142_IOMUX_UART1_TXD 0 +#define GPIO_142_IOMUX_GPIOxx 1 +#define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0 +#define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1 +#define GPIO_145_IOMUX_SMBUS0_SCL 2 +#define GPIO_145_IOMUX_GPIOxx 3 +#define GPIO_146_IOMUX_I3C0_SDA_SPD0_SDA 0 +#define GPIO_146_IOMUX_I2C0_SDA_SPD0_SDA 1 +#define GPIO_146_IOMUX_SMBUS0_SDA 2 +#define GPIO_146_IOMUX_GPIOxx 3 +#define GPIO_147_IOMUX_I3C1_SCL_SPD1_SCL 0 +#define GPIO_147_IOMUX_I2C1_SCL_SPD1_SCL 1 +#define GPIO_147_IOMUX_GPIOxx 2 +#define GPIO_148_IOMUX_I3C1_SDA_SPD1_SDA 0 +#define GPIO_148_IOMUX_I2C1_SDA_SPD1_SDA 1 +#define GPIO_148_IOMUX_GPIOxx 2 +#define GPIO_149_IOMUX_I3C2_SCL_SPD2_SCL 0 +#define GPIO_149_IOMUX_I2C2_SCL_SPD2_SCL 1 +#define GPIO_149_IOMUX_GPIOxx 2 +#define GPIO_150_IOMUX_I3C2_SDA_SPD2_SDA 0 +#define GPIO_150_IOMUX_I2C2_SDA_SPD2_SDA 1 +#define GPIO_150_IOMUX_GPIOxx 2 +#define GPIO_151_IOMUX_I3C3_SCL_SPD3_SCL 0 +#define GPIO_151_IOMUX_I2C3_SCL_SPD3_SCL 1 +#define GPIO_151_IOMUX_GPIOxx 2 +#define GPIO_152_IOMUX_I3C3_SDA_SPD3_SDA 0 +#define GPIO_152_IOMUX_I2C3_SDA_SPD3_SDA 1 +#define GPIO_152_IOMUX_GPIOxx 2 + +/* Remote GPIOs */ +#define GPIO_256_IOMUX_GPIOxx 0 +#define GPIO_257_IOMUX_GPIOxx 0 +#define GPIO_258_IOMUX_GPIOxx 0 +#define GPIO_259_IOMUX_GPIOxx 0 +#define GPIO_260_IOMUX_GPIOxx 1 +#define GPIO_261_IOMUX_GPIOxx 1 +#define GPIO_264_IOMUX_GPIOxx 1 +#define GPIO_265_IOMUX_GPIOxx 1 +#define GPIO_266_IOMUX_GPIOxx 1 + +#endif /* AMD_GENOA_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Gerrit-Change-Number: 78220 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/genoa: Enable uart
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76507?usp=email ) Change subject: soc/amd/genoa: Enable uart ...................................................................... soc/amd/genoa: Enable uart Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 --- M src/mainboard/amd/onyx/Kconfig M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/uart.h A src/soc/amd/genoa/uart.c 6 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/76507/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Gerrit-Change-Number: 76507 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd/genoa: Enable eSPI early
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Martin L Roth. Varshit Pandya has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76508?usp=email ) Change subject: soc/amd/genoa: Enable eSPI early ...................................................................... soc/amd/genoa: Enable eSPI early Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 --- M src/mainboard/amd/onyx/devicetree.cb M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/acpi.h A src/soc/amd/genoa/include/soc/lpc.h A src/soc/amd/genoa/include/soc/pci_devs.h 6 files changed, 91 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/76508/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/76508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Gerrit-Change-Number: 76508 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd/genoa: Add aoac.c & enable AOAC devices early
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Martin L Roth. Varshit Pandya has uploaded a new patch set (#9) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76506?usp=email ) Change subject: soc/amd/genoa: Add aoac.c & enable AOAC devices early ...................................................................... soc/amd/genoa: Add aoac.c & enable AOAC devices early Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 --- M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/aoac.c M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/aoac_defs.h 4 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/76506/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/76506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Gerrit-Change-Number: 76506 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/genoa: Enable PM and cf9 IO early
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth. Varshit Pandya has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email ) The following approvals got outdated and were removed: Code-Review-1 by Felix Held Change subject: soc/amd/genoa: Enable PM and cf9 IO early ...................................................................... soc/amd/genoa: Enable PM and cf9 IO early Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/early_fch.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/76505/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Gerrit-Change-Number: 76505 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: MAINTAINERS: Add Brya maintainer
by Subrata Banik (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78219?usp=email ) Change subject: MAINTAINERS: Add Brya maintainer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2bd5d9e9c93cf09ce4bca6a55cb5fab137f1bbc Gerrit-Change-Number: 78219 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 13:50:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Brya maintainer
by Eric Lai (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78219?usp=email ) Change subject: MAINTAINERS: Add Brya maintainer ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Testing :p -- To view, visit https://review.coreboot.org/c/coreboot/+/78219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2bd5d9e9c93cf09ce4bca6a55cb5fab137f1bbc Gerrit-Change-Number: 78219 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 13:47:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex: Configure ISH UART TX/RX as NC
by Kapil Porwal (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Bernardo Perez Priego, Cliff Huang, Eran Mitrani, Jakub Czapiga, Li1 Feng, Tarun. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78049?usp=email ) Change subject: mb/google/rex: Configure ISH UART TX/RX as NC ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8aba45420744a3990e1f9637c3b31ea2e0f78f87 Gerrit-Change-Number: 78049 Gerrit-PatchSet: 4 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 11:40:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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