coreboot-gerrit October 2023

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[S] Change in coreboot[main]: mb/starlabs/starbook/{adl,rpl}: Enable the CNVi device
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78197?usp=email ) Change subject: mb/starlabs/starbook/{adl,rpl}: Enable the CNVi device ...................................................................... mb/starlabs/starbook/{adl,rpl}: Enable the CNVi device Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78197 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index dc767d2..ed48757 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -87,6 +87,13 @@ end end device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref heci1 on end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index b319f5e..976f990 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -107,6 +107,13 @@ end end device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref heci1 on end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/78197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f Gerrit-Change-Number: 78197 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[NoOp] Change in coreboot[main]: mb/starlabs/starbook/rpl: Update the VBT to 251
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78196?usp=email ) Change subject: mb/starlabs/starbook/rpl: Update the VBT to 251 ...................................................................... mb/starlabs/starbook/rpl: Update the VBT to 251 Updating FSP to v4301.01 caused a strange flicker when connecting an external display. Update the VBT to 251 from 242 with the exact same settings to resolve this. Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78196 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/rpl/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt index 8ecfffb..f299aa5 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/data.vbt +++ b/src/mainboard/starlabs/starbook/variants/rpl/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/78196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a Gerrit-Change-Number: 78196 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Update the Q Events
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77405?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/starlabs/merlin: Update the Q Events ...................................................................... ec/starlabs/merlin: Update the Q Events Simplify the Q events for the battery and charger to just notify when a status has changed. The EC will trigger these events when either has changed. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3300be5254549fe5cd3b3490d9191240c6d36b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77405 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/variants/merlin/events.asl 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/starlabs/merlin/variants/merlin/events.asl b/src/ec/starlabs/merlin/variants/merlin/events.asl index acfb6be..38a4971 100644 --- a/src/ec/starlabs/merlin/variants/merlin/events.asl +++ b/src/ec/starlabs/merlin/variants/merlin/events.asl @@ -10,15 +10,13 @@ ^^^^HIDD.HPEM (19) } -Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +Method (_Q0A, 0, NotSerialized) // Event: Charger Status Update { - Notify (BAT0, 0x81) Notify (ADP1, 0x80) } -Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +Method (_Q0B, 0, NotSerialized) // Event: Battery Information Update { - Notify (BAT0, 0x81) Notify (BAT0, 0x80) } -- To view, visit https://review.coreboot.org/c/coreboot/+/77405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3300be5254549fe5cd3b3490d9191240c6d36b6e Gerrit-Change-Number: 77405 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd: rework SPL file override and SPL fusing handling
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78178?usp=email ) Change subject: soc/amd: rework SPL file override and SPL fusing handling ...................................................................... soc/amd: rework SPL file override and SPL fusing handling The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a way to override the default SPL file configured in the SoC's fw.cfg file by passing the '--spl-table' parameter to amdfwtool which will then use the override instead of the SPL file from the fw.cfg file. When SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix call in the makefile will result in no '--spl-table' parameter being passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In order to not pass an SPL override by default, remove the default from the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the same SPL file as in fw.cfg file anyway. Now only when a mainboard sets this option to point to a file, that file will be used as an override. This override is used to include a special SPL file needed for the verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an empty string by default, neither the SPL_TABLE_FILE Kconfig option nor it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE, so remove the dependency in the Kconfig and the ifeq in the Makefile. Before this patch, the HAVE_SPL_FILE option controlled two things that shouldn't be controlled by the same Kconfig option: Only when HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into account, and it also controls if spl_fuse.c got added to the build which when added will send the SPL fusing command to the PSP. So the case of needing an SPL file override, but not updating the SPL fuses wasn't supported before. The SPL file in the amdfw part will be used by the PSP bootloader for the anti-rollback feature which makes sure that the SPL file version isn't lower than what is in the SPL fuses. For this the SPL file needs to be present in the PSP directory table. The SPL version check happens way before we're running code on the x86 cores. The SPL fusing PSP command that can be sent by coreboot will tell the PSP to update the SPL fuses so that the fused minimal SPL version will be updated to the current SPL version. Since the former HAVE_SPL_FILE option now only controls if the SPL fusing command will be sent to the PSP mailbox, rename it to PERFORM_SPL_FUSING to clarify what this will do and update the help text correctly describe what this does. TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman with Phoenix APU and Skyrim result in identical binaries. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78178 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/skyrim/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 13 files changed, 88 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7f233be..30d9277 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -106,13 +106,12 @@ string default "src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg" -config HAVE_SPL_FILE +config PERFORM_SPL_FUSING bool default y config SPL_TABLE_FILE string - depends on HAVE_SPL_FILE default "3rdparty/blobs/mainboard/google/guybrush/TypeId0x55_SplTable_Prod_CZN_Chrome.sbin" if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 59f6c67..06119e0 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -96,13 +96,12 @@ depends on CHROMEOS default y -config HAVE_SPL_FILE +config PERFORM_SPL_FUSING bool default y config SPL_TABLE_FILE string - depends on HAVE_SPL_FILE default "3rdparty/blobs/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin" config HAVE_SPL_RW_AB_FILE @@ -111,7 +110,6 @@ config SPL_RW_AB_TABLE_FILE string - depends on HAVE_SPL_RW_AB_FILE default "3rdparty/blobs/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME.sbin" config SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 160bc65..ca84b33 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -376,19 +376,27 @@ depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific SPL table file, which is created by AMD - and put to 3rdparty/blobs. + Send the Security Patch Level (SPL) fusing command to the PSP in + order to update the minimum SPL version to be written to the SoC's + fuse bits. This will prevent using any embedded firmware components + with lower SPL version. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 76cb9e8..c92bb0d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -91,9 +91,7 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 0f15963..a89d4e9 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -29,6 +29,6 @@ smm-y += psp_gen2.c smm-y += psp_smm_gen2.c -ramstage-$(CONFIG_HAVE_SPL_FILE) += spl_fuse.c +ramstage-$(CONFIG_PERFORM_SPL_FUSING) += spl_fuse.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index c4f8a9d..9863a59 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -117,13 +117,27 @@ string "Debug whitelist file path" depends on HAVE_PSP_WHITELIST_FILE -config HAVE_SPL_FILE - bool +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" + default n + help + Send the Security Patch Level (SPL) fusing command to the PSP in + order to update the minimum SPL version to be written to the SoC's + fuse bits. This will prevent using any embedded firmware components + with lower SPL version. + + If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index efbd3b1..6b936b6 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -46,9 +46,7 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index ae4b190..9f5d537 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -349,37 +349,38 @@ depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/glinda/PSP/wtl-mrg.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific Security Patch Level (SPL) table file. SPL file - is required to support PSP FW anti-rollback and needs to be created by AMD. - The default SPL file applies to all boards that use the concerned SoC and - is dropped under 3rdparty/blobs. The mainboard specific SPL file override - can be applied through SPL_TABLE_FILE config. + Send the Security Patch Level (SPL) fusing command to the PSP in + order to update the minimum SPL version to be written to the SoC's + fuse bits. This will prevent using any embedded firmware components + with lower SPL version. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n - depends on HAVE_SPL_FILE depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table - file for the RW A/B FMAP partitions. See the help text of - HAVE_SPL_FILE for a more detailed description. + file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE - string "Separate SPL table file for RW A/B partitions" - depends on HAVE_SPL_RW_AB_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin" + string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 25b2fe4..ea2a48b 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -86,14 +86,12 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) else SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) endif -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d179f35..ba20481 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -406,37 +406,38 @@ depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/mendocino/PSP/wtl-mdn.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific Security Patch Level (SPL) table file. SPL file - is required to support PSP FW anti-rollback and needs to be created by AMD. - The default SPL file applies to all boards that use the concerned SoC and - is dropped under 3rdparty/blobs. The mainboard specific SPL file override - can be applied through SPL_TABLE_FILE config. + Send the Security Patch Level (SPL) fusing command to the PSP in + order to update the minimum SPL version to be written to the SoC's + fuse bits. This will prevent using any embedded firmware components + with lower SPL version. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n - depends on HAVE_SPL_FILE depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table - file for the RW A/B FMAP partitions. See the help text of - HAVE_SPL_FILE for a more detailed description. + file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE - string "Separate SPL table file for RW A/B partitions" - depends on HAVE_SPL_RW_AB_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" + string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 14eb363..9442083 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -89,14 +89,12 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) else SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) endif -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 18ed58f..ec1a9e9 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -361,37 +361,38 @@ depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin" -config HAVE_SPL_FILE - bool "Have a mainboard specific SPL table file" +config PERFORM_SPL_FUSING + bool "Send SPL fuse command to PSP" default n help - Have a mainboard specific Security Patch Level (SPL) table file. SPL file - is required to support PSP FW anti-rollback and needs to be created by AMD. - The default SPL file applies to all boards that use the concerned SoC and - is dropped under 3rdparty/blobs. The mainboard specific SPL file override - can be applied through SPL_TABLE_FILE config. + Send the Security Patch Level (SPL) fusing command to the PSP in + order to update the minimum SPL version to be written to the SoC's + fuse bits. This will prevent using any embedded firmware components + with lower SPL version. If unsure, answer 'n' config SPL_TABLE_FILE - string "SPL table file" - depends on HAVE_SPL_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin" + string "SPL table file override" + help + Provide a mainboard-specific Security Patch Level (SPL) table file + override. The SPL file is required to support PSP FW anti-rollback + and needs to be created by AMD. The default SPL file specified in the + SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule + and applies to all boards that use the SoC without verstage on PSP. + In the verstage on PSP case, a different SPL file is specific as an + override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n - depends on HAVE_SPL_FILE depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table - file for the RW A/B FMAP partitions. See the help text of - HAVE_SPL_FILE for a more detailed description. + file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE - string "Separate SPL table file for RW A/B partitions" - depends on HAVE_SPL_RW_AB_FILE - default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin" + string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index b2f566d..d589bf1 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -92,14 +92,12 @@ endif # type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) else SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) endif -endif # # BIOS Directory Table items - proper ordering is managed by amdfwtool -- To view, visit https://review.coreboot.org/c/coreboot/+/78178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Gerrit-Change-Number: 78178 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/uldren: Remove fw_config probe for TS and TP
by Derek Huang (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Dtrain Hsu, Nick Vaccaro, Subrata Banik. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77538?usp=email ) Change subject: mb/google/nissa/var/uldren: Remove fw_config probe for TS and TP ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f12ae478f74c019c53ee5e77f7e0f9c324e758 Gerrit-Change-Number: 77538 Gerrit-PatchSet: 6 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Oct 2023 08:55:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/quandiso: Fix touchscreen probed flag
by Derek Huang (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Martin L Roth, Nick Vaccaro, Reka Norman, Robert Chen, Shawn Ku, Subrata Banik. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78167?usp=email ) Change subject: mb/google/nissa/var/quandiso: Fix touchscreen probed flag ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78167/comment/4bfa77df_ebac0dec : PS1, Line 9: detect flag isn't ready in firmware-nissa-15217.B Are you sure? Some nissa variants use detect flags in nissa firmware branch already. -- To view, visit https://review.coreboot.org/c/coreboot/+/78167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I674b636e1c5d8554ba91d380c61d381d7db95054 Gerrit-Change-Number: 78167 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Derek Huang <derekhuang(a)google.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shawn Ku <shawnku(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Oct 2023 08:39:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi.c: Fix generating pointer to cb_tables located >4G
by Arthur Heymans (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Benjamin Doron, Eric Lai, Felix Held, Lance Zhao, Maximilian Brune, Nico Huber, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76181?usp=email ) Change subject: acpi.c: Fix generating pointer to cb_tables located >4G ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > Agree with Nico. I'm not sure what you mean. There is no 64bit equivalent of Memory32Fixed in ACPI. -- To view, visit https://review.coreboot.org/c/coreboot/+/76181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1bc553b18d08cee502b765166227810f8e619631 Gerrit-Change-Number: 76181 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 07:16:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Add THERMAL_SOLUTION field in fw_config
by Tyler Wang (Code Review) 04 Oct '23

04 Oct '23

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78216?usp=email ) Change subject: mb/google/rex/var/karis: Add THERMAL_SOLUTION field in fw_config ...................................................................... mb/google/rex/var/karis: Add THERMAL_SOLUTION field in fw_config Bit 6-7, THERMAL_SOLUTION, 0 --> THERMAL_SOLUTION_1 BUG=b:290689824, b:294155897 TEST=emerge-rex coreboot Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/overridetree.cb 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/78216/1 diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index 98769de..e6e7072 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -6,6 +6,9 @@ field AUDIO 3 5 option ALC5650_NO_AMP_I2S 0 end + field THERMAL_SOLUTION 6 7 + option THERMAL_SOLUTION_1 0 + end field MIPI_CAM 8 9 option UF_CAM_HI556 0 end @@ -237,7 +240,9 @@ register "options.fan.fine_grained_control" = "1" register "options.fan.step_size" = "2" - device generic 0 alias dptf_policy on end + device generic 0 alias dptf_policy on + probe THERMAL_SOLUTION THERMAL_SOLUTION_1 + end end end device ref pcie_rp10 on -- To view, visit https://review.coreboot.org/c/coreboot/+/78216?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b Gerrit-Change-Number: 78216 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ix
by Eric Lai (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Nick Vaccaro, SH Kim, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77998?usp=email ) Change subject: mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ix ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > The behavior is like unplug at suspend and then plug-in again at resume. […] LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/77998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c Gerrit-Change-Number: 77998 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Oct 2023 06:22:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ix
by SH Kim (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77998?usp=email ) Change subject: mb/google/nissa/var/pirrha: Turn off SD card power signal in s0ix ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Please verify with open the storage in the OS before suspend. The behavior is like unplug at suspend and then plug-in again at resume. I think it's expected since this change makes SD card controller to be powered off in s0ix. 1. Open "Files" app and navigate to SD card 2. Run suspend_stress_test -c 1 on VT2 3. See current directory of "Files" app Result: "Files" app shows "My Files" directory. -- To view, visit https://review.coreboot.org/c/coreboot/+/77998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c Gerrit-Change-Number: 77998 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Oct 2023 06:15:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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