coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[XS] Change in coreboot[main]: mb/amd/onyx: Use BMC SOL by default
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76509?usp=email ) Change subject: mb/amd/onyx: Use BMC SOL by default ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: We want to wait and submit this with the rest of this patch train. -- To view, visit https://review.coreboot.org/c/coreboot/+/76509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefe61d25367bbe5cff0cacbfbafa32607de77d0f Gerrit-Change-Number: 76509 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:29:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel: Move USB wake methods to a common ASL file
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78085?usp=email ) Change subject: soc/intel: Move USB wake methods to a common ASL file ...................................................................... soc/intel: Move USB wake methods to a common ASL file The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/soc/intel/alderlake/acpi/xhci.asl M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/include/soc/usb.h M src/soc/intel/cannonlake/acpi/xhci.asl M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/usb.h A src/soc/intel/common/acpi/xhci_wake.asl M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/usb.h 11 files changed, 65 insertions(+), 156 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index e4001fe..1c3bbbe 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include <intelblocks/xhci.h> #include <soc/gpe.h> -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 &= PORTSCN_BITS_OFF_MASK - Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 &= (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl> /* XHCI Controller 0:14.0 */ diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 65d6e85..b1e90fa 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -12,6 +12,7 @@ #include <intelblocks/power_limit.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/tcss.h> +#include <intelblocks/xhci.h> #include <soc/gpe.h> #include <soc/pci_devs.h> #include <soc/pmc.h> diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 2a701c8..b84cce7 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -163,11 +163,4 @@ .ocpin = (pin), \ } -/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 0f8f51f..beaa843 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include <intelblocks/xhci.h> #include <soc/gpe.h> -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 = Local0 & PORTSCN_BITS_OFF_MASK - Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 = Local0 & (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl> /* XHCI Controller 0:14.0 */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3093050..994f2ae 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -10,6 +10,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/power_limit.h> +#include <intelblocks/xhci.h> #include <stdbool.h> #include <stdint.h> #include <soc/pch.h> diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 20b3149..3f020ef 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -186,11 +186,4 @@ .gen2_rx_filter_sel = 0x44, \ } -/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif diff --git a/src/soc/intel/common/acpi/xhci_wake.asl b/src/soc/intel/common/acpi/xhci_wake.asl new file mode 100644 index 0000000..e029a6f --- /dev/null +++ b/src/soc/intel/common/acpi/xhci_wake.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/xhci.h> + +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + Local0 = Arg1 + ((Arg0 - 1) * 0x10) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) + Field (PSCR, DWordAcc, NoLock, Preserve) + { + PSCT, 32, + } + Local0 = PSCT + Local0 &= PORTSCN_BITS_OFF_MASK + Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE + PSCT = Local0 +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Local0 = Arg0 + + While (1) { + FindSetRightBit (Local0, Local1) + If (Local1 == 0) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + */ + Local0 &= (Local0 - 1) + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 15b16d2..1a72e0f 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -16,6 +16,13 @@ #define PORTSCN_BITS_OFF_MASK ~0x80FE0012 #define PORTSCXUSB3_OFFSET 0x540 +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) + #if !defined(__ACPI__) #include <device/device.h> #include <device/xhci.h> diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 0540919..bfe6c6d 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -2,51 +2,8 @@ #include <intelblocks/xhci.h> -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 = Local0 & PORTSCN_BITS_OFF_MASK - Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 = Local0 & (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl> /* XHCI Controller 0:14.0 */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 5119037..3070c46 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -12,6 +12,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/power_limit.h> +#include <intelblocks/xhci.h> #include <stdbool.h> #include <stdint.h> #include <soc/gpe.h> diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index 7912603..612ad5f 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -180,11 +180,4 @@ .tx_downscale_amp = 0x00, \ } -/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/78085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Gerrit-Change-Number: 78085 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/amd/genoa: Enable eSPI early
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76508?usp=email ) Change subject: soc/amd/genoa: Enable eSPI early ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76508/comment/66720986_049ba8f0 : PS5, Line 21: This line was removed in an earlier patch, so it'll probably need a manual rebase after it's restored there. -- To view, visit https://review.coreboot.org/c/coreboot/+/76508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Gerrit-Change-Number: 76508 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/amd/genoa: Add aoac.c & enable AOAC devices early
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth, Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76506?usp=email ) Change subject: soc/amd/genoa: Add aoac.c & enable AOAC devices early ...................................................................... Patch Set 9: (1 comment) File src/soc/amd/genoa/aoac.c: https://review.coreboot.org/c/coreboot/+/76506/comment/761b1f14_93532b16 : PS9, Line 22: 100 Do we know why this value was chosen, or what the typical amount of time is? Can this be smaller? -- To view, visit https://review.coreboot.org/c/coreboot/+/76506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Gerrit-Change-Number: 76506 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:26:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/genoa: Enable PM and cf9 IO early
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth, Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email ) Change subject: soc/amd/genoa: Enable PM and cf9 IO early ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76505/comment/e4bc2f99_ae16cb16 : PS8, Line 18: > i'd keep this empty line Agreed, and then there aren't any changes to this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/76505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Gerrit-Change-Number: 76505 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:24:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/common/vboot: Fix the PSP verstage timestamps
by Tim Van Patten (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Martin Roth, Matt DeVillier. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78231?usp=email ) Change subject: soc/amd/common/vboot: Fix the PSP verstage timestamps ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/common/vboot/vboot_bootblock.c: https://review.coreboot.org/c/coreboot/+/78231/comment/8d5dd396_0f0c2841 : PS1, Line 48: * We ignore the time between x86 processor release and bootblock. : * Since timestamp_add subtracts base_time, we first add old base_time : * to make it absolute then add base_timestamp again since : * it'll be a new base_time. It looks like this needs to be updated to describe why `tse->entry_stamp` is added also. -- To view, visit https://review.coreboot.org/c/coreboot/+/78231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e52bef22f65596152f29c511bed680427660ff5 Gerrit-Change-Number: 78231 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/genoa: Enable PM and cf9 IO early
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Martin L Roth, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email ) Change subject: soc/amd/genoa: Enable PM and cf9 IO early ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76505/comment/3e274336_e098096b : PS8, Line 18: i'd keep this empty line -- To view, visit https://review.coreboot.org/c/coreboot/+/76505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Gerrit-Change-Number: 76505 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:12:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/amd/genoa: Enable eSPI early
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin Roth. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76508?usp=email ) Change subject: soc/amd/genoa: Enable eSPI early ...................................................................... Patch Set 5: (4 comments) File src/mainboard/amd/onyx/devicetree.cb: https://review.coreboot.org/c/coreboot/+/76508/comment/90e4b766_03e35966 : PS4, Line 19: device cpu_cluster 0 on end > not needed, since we already have that in the chipset devicetree Done File src/soc/amd/genoa/Kconfig: https://review.coreboot.org/c/coreboot/+/76508/comment/5170d2a3_ba725e9b : PS3, Line 27: > Nit: remove extra line? Done File src/soc/amd/genoa/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/76508/comment/224bcc94_19d9a749 : PS3, Line 5: > might be good to remove this second empty line Done https://review.coreboot.org/c/coreboot/+/76508/comment/b8420d14_a451a8e3 : PS3, Line 21: > oh, looks like the common lpc_util has its own definition for the lpc device Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Gerrit-Change-Number: 76508 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:10:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/amd/genoa: Add aoac.c & enable AOAC devices early
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth, Martin Roth. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76506?usp=email ) Change subject: soc/amd/genoa: Add aoac.c & enable AOAC devices early ...................................................................... Patch Set 9: (3 comments) File src/soc/amd/genoa/aoac.c: https://review.coreboot.org/c/coreboot/+/76506/comment/5d5418e1_73ee03c9 : PS4, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > Note that this file no longer exists in the preceding commits, so this patch needs to be rebased man […] Done https://review.coreboot.org/c/coreboot/+/76506/comment/2cac664a_0304bff6 : PS4, Line 12: : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ > uart2 is missing here Done File src/soc/amd/genoa/include/soc/aoac_defs.h: https://review.coreboot.org/c/coreboot/+/76506/comment/cf8463ba_f2c7921b : PS7, Line 17: #define FCH_AOAC_DEV_UART3 26 : #define FCH_AOAC_DEV_UART4 20 > does genoa have uart3 and 4? from the devicetree i'd assume that it has only uarts 0.. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Gerrit-Change-Number: 76506 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:10:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/genoa: Enable PM and cf9 IO early
by Varshit Pandya (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email ) Change subject: soc/amd/genoa: Enable PM and cf9 IO early ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/genoa/early_fch.c: https://review.coreboot.org/c/coreboot/+/76505/comment/275ea8ed_64481d9a : PS2, Line 16: enable_acpimmio_decode_pm04(); > i read the ppr like that this won't work, so i wouldn't select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_A […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Gerrit-Change-Number: 76505 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:07:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023