coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/pch: Mark static devices hidden
by Kyösti Mälkki (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78230?usp=email ) Change subject: sb/intel/bd82x6x/pch: Mark static devices hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Technically when the system is in S3 PCIe devices are cold plugged. I would assume it works fine. My concern was about the enumeration process potentially assigning different bus numbers for S3 resume path, in comparison to normal boot path. I believe there were thunderbolt-related changes, where any hotplug-capable rootport always makes reserves for a range of secondary-side bus numbers and IO/MMIO spaces, and this avoid such problem. There are some cases, when normal boot path records the assigned PCI bus number (or the complete PCI BDF) of a device as a static entry. These would no longer evaluate correctly after S3 resume. AMD IVRS / IVHD comes to mind now. -- To view, visit https://review.coreboot.org/c/coreboot/+/78230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a Gerrit-Change-Number: 78230 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 18:51:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cmn/gfx: Add API to report presence of external display
by Subrata Banik (Code Review) 04 Oct '23

04 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78080?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/cmn/gfx: Add API to report presence of external display ...................................................................... soc/intel/cmn/gfx: Add API to report presence of external display This patch implements an API to report the presence of an external display on Intel silicon. The API uses information from the transcoder and framebuffer to determine if an external display is connected. For example, if the transcoder is attached to any DDI ports other than DDI-A (eDP), and the framebuffer is initialized, then it is likely that an external display is present. This information can be used by payloads to determine whether or not to power on the display, even if eDP is not initialized. BUG=b:299137940 TEST=Build and boot google/rex Scenarios: Booting with eDP alone: has_external_display value is 0 Booting with eDP + HDMI: has_external_display value is 0 Booting with HDMI alone: has_external_display value is 1 Booting with USB-C display alone: has_external_display value is 1 Change-Id: I77436940978c7fa9368d79394b46a5e794c32e42 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78080 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 50 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Julius Werner: Looks good to me, approved Nick Vaccaro: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 69754fd..5b2484a 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -31,6 +31,56 @@ return NULL; } +/* + * Transcoders contain the timing generators for eDP, DP, and HDMI interfaces. + * Intel transcoders are based on Quick Sync Video, which offloads video + * encoding and decoding tasks from the CPU to the GPU. + * + * On Intel silicon, there are four display pipes (DDI-A to DDI-D) that support + * blending, color adjustments, scaling, and dithering. + * + * From the display block diagram perspective, the front end of the display + * contains the pipes. The pipes connect to the transcoder. The transcoder + * (except for wireless) connects to the DDIs to drive the IO/PHY. + * + * This logic checks if the DDI-A port is attached to the transcoder and + * enabled (bit 27). Traditionally, the on-board display (eDP) is attached to DDI-A. + * If the above conditions is met, then the on-board display is present and enabled. + * + * On platforms without an on-board display (i.e., value at bits 27-30 is between 2-9), + * meaning that DDI-A (eDP) is not enabled. + * + * Additionally, if bits 27-30 are all set to 0, this means that no DDI ports + * are enabled, and there is no display. + * + * Consider external display is present and enabled, if eDP/DDI-A is not enabled + * and transcoder is attached to any DDI port (bits 27-30 are not zero). + */ +static int get_external_display_status(void) +{ + uint32_t ddi_func_ctrl = graphics_gtt_read(TRANS_DDI_FUNC_CTL_A); + ddi_func_ctrl &= TRANS_DDI_PORT_MASK; + + /* + * Check if transcoder is none or connected to DDI-A port (aka eDP). + * Report no external display in both cases. + */ + if (ddi_func_ctrl == TRANS_DDI_PORT_NONE) { + return 0; + } else { + if (ddi_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A)) + return 0; + else + return 1; + } +} + +/* Check and report if an external display is attached */ +int fsp_soc_report_external_display(void) +{ + return graphics_get_framebuffer_address() && get_external_display_status(); +} + static void gma_init(struct device *const dev) { intel_gma_init_igd_opregion(); -- To view, visit https://review.coreboot.org/c/coreboot/+/78080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77436940978c7fa9368d79394b46a5e794c32e42 Gerrit-Change-Number: 78080 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: {commonlib, libpayload}: Add "has_external_display" in coreboot table
by Subrata Banik (Code Review) 04 Oct '23

04 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77796?usp=email ) Change subject: {commonlib, libpayload}: Add "has_external_display" in coreboot table ...................................................................... {commonlib, libpayload}: Add "has_external_display" in coreboot table This patch introduces a new coreboot table entry named "has_external_display" to understand if external display is attached. This information is useful to prevent graceful shutdown by payload when the LID is closed but an external display is present. This piece of the information will be gathered by coreboot and passed into the payload using this new entry aka external_display because payload (i.e., deptcharge) doesn't have any other way to determine if external display is available. BUG=b:299137940 TEST=Able to build and boot google/rex. w/o this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > System is powered off by depthcharge w/ this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > Booted to OS and device is alive/usable Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77796 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/fsp2_0/graphics.c M src/drivers/intel/fsp2_0/include/fsp/graphics.h 4 files changed, 34 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 4502e34..5c3f0c4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -220,6 +220,11 @@ CB_FB_ORIENTATION_RIGHT_UP = 3, }; +struct cb_framebuffer_flags { + u8 has_external_display : 1; + u8 reserved : 7; +}; + struct cb_framebuffer { u32 tag; u32 size; @@ -238,6 +243,8 @@ u8 reserved_mask_pos; u8 reserved_mask_size; u8 orientation; + struct cb_framebuffer_flags flags; + u8 pad; }; #define CB_GPIO_ACTIVE_LOW 0 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index d77c5eb..94985b1 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -275,6 +275,11 @@ LB_FB_ORIENTATION_RIGHT_UP = 3, }; +struct lb_framebuffer_flags { + uint8_t has_external_display : 1; + uint8_t reserved : 7; +}; + struct lb_framebuffer { uint32_t tag; uint32_t size; @@ -293,7 +298,8 @@ uint8_t reserved_mask_pos; uint8_t reserved_mask_size; uint8_t orientation; - uint8_t pad[2]; + struct lb_framebuffer_flags flags; + uint8_t pad; }; struct lb_gpio { diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 6514209..a98f3bb 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -54,6 +54,13 @@ FW_SPLASH_SCREEN_ENABLED, }; +/* Check and report if an external display is attached */ +__weak int fsp_soc_report_external_display(void) +{ + /* Default implementation, on-board display enabled */ + return 0; +} + /* * Update elog with Firmware Splash Screen related information * based on enum fw_splash_screen_status. @@ -123,6 +130,9 @@ .reserved_mask_pos = fbinfo->rsvd.pos, .reserved_mask_size = fbinfo->rsvd.size, .orientation = orientation, + .flags = { + .has_external_display = fsp_soc_report_external_display(), + }, }; fb_add_framebuffer_info_ex(&fb); diff --git a/src/drivers/intel/fsp2_0/include/fsp/graphics.h b/src/drivers/intel/fsp2_0/include/fsp/graphics.h index dfd7b4e..a5f781f 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/graphics.h +++ b/src/drivers/intel/fsp2_0/include/fsp/graphics.h @@ -14,4 +14,14 @@ void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar, enum lb_fb_orientation orientation); +/* SoC Overrides */ +/* + * Check and report if an external display is attached + * + * Possible return values: + * 1 - An external device is attached. + * 0 - On-board display alone. + */ +int fsp_soc_report_external_display(void); + #endif /* _FSP2_0_GRAPHICS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/77796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Gerrit-Change-Number: 77796 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs
by Subrata Banik (Code Review) 04 Oct '23

04 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78079?usp=email ) Change subject: soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs ...................................................................... soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/tigerlake/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 038d57c..82ec8f2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -29,6 +29,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 + select INTEL_GMA_VERSION_2 select INTEL_TXT_LIB select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 28618f6..48030a1 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -31,6 +31,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 + select INTEL_GMA_VERSION_2 select IOAPIC select MICROCODE_BLOB_UNDISCLOSED select MP_SERVICES_PPI_V2 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index df8f5a2..0a4b7bf 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -29,6 +29,7 @@ select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select INTEL_GMA_VERSION_2 select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK -- To view, visit https://review.coreboot.org/c/coreboot/+/78079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Gerrit-Change-Number: 78079 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/gma: Update port select bit definitions
by Subrata Banik (Code Review) 04 Oct '23

04 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78078?usp=email ) Change subject: drivers/intel/gma: Update port select bit definitions ...................................................................... drivers/intel/gma: Update port select bit definitions This commit updates the port select bit definitions for the TRANS_DDI_FUNC_CTL registers in the Intel GMA driver to accommodate the changes introduced since TGL SoC. Specifically, the following changes were made: - Updated the DDI select bit definitions from 3-bits (bit 28-30) to 4-bits (bit 27-30). - Introduces `INTEL_GMA_VERSION_2` config to accommodate the port and pipe related differences between previous generation GMA register (TRANS_DDI_FUNC_CTL) to the current generation GMA register. This commit backports the change from the following upstream patch: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-3- lucas.demarchi(a)intel.com BUG=b:299137940 TEST=Able to build and boot google/rex. Change-Id: I815ffa90c2e235afd70baa7e3837e1f9af89b1b0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/i915.h M src/drivers/intel/gma/i915_reg.h 3 files changed, 36 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index d1e16e2..e6704f0 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -122,6 +122,22 @@ bool default n +config INTEL_GMA_VERSION_2 + bool + default n + help + Intel display port and pipe related register definitions have changed since + Tiger Lake SoC. This option enables support for the updated `TRANS_DDI_FUNC_CTL` + register definitions. + + SoCs that support Intel GMA Version 2 include: + * Alder Lake + * Meteor Lake + * Tiger Lake + + If you are unsure whether your SoC supports Intel GMA Version 2, it is safe to + disable this option. + if GFX_GMA || EARLY_GFX_GMA config GFX_GMA_DYN_CPU diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 8e9fc90..5c34104 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -30,6 +30,12 @@ PORT_A = 0, PORT_B, PORT_C, +#if CONFIG(INTEL_GMA_VERSION_2) + PORT_USB_C1, + PORT_USB_C2, + PORT_USB_C3, + PORT_USB_C4, +#endif PORT_D, PORT_E, I915_NUM_PORTS @@ -39,6 +45,9 @@ PIPE_A = 0, PIPE_B, PIPE_C, +#if CONFIG(INTEL_GMA_VERSION_2) + PIPE_D, +#endif I915_NUM_PIPES }; diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8a7ccf7..3d6cd45 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4181,9 +4181,17 @@ TRANS_DDI_FUNC_CTL_B) #define TRANS_DDI_FUNC_ENABLE (1UL<<31) /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ -#define TRANS_DDI_PORT_MASK (7<<28) -#define TRANS_DDI_SELECT_PORT(x) ((x)<<28) -#define TRANS_DDI_PORT_NONE (0<<28) +#if CONFIG(INTEL_GMA_VERSION_2) +#define TRANS_DDI_PORT_SHIFT 27 +#define TRANS_DDI_PORT_WIDTH 0xf +#define TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TRANS_DDI_PORT_SHIFT) +#else +#define TRANS_DDI_PORT_SHIFT 28 +#define TRANS_DDI_PORT_WIDTH 7 +#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) +#endif +#define TRANS_DDI_PORT_MASK (TRANS_DDI_PORT_WIDTH << TRANS_DDI_PORT_SHIFT) +#define TRANS_DDI_PORT_NONE (0 << TRANS_DDI_PORT_SHIFT) #define TRANS_DDI_MODE_SELECT_MASK (7<<24) #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) #define TRANS_DDI_MODE_SELECT_DVI (1<<24) -- To view, visit https://review.coreboot.org/c/coreboot/+/78078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I815ffa90c2e235afd70baa7e3837e1f9af89b1b0 Gerrit-Change-Number: 78078 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Use helper for PCIe hotplug
by Patrick Rudolph (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78227?usp=email ) Change subject: sb/intel/bd82x6x: Use helper for PCIe hotplug ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/bd82x6x/pcie.c: https://review.coreboot.org/c/coreboot/+/78227/comment/662763f1_a4c16ebd : PS1, Line 213: pci_write_config16(dev, 0x42, 0x142); > Not in this commit, but we had a define for register 0x42 to previously set the SI Slot Implemented […] Good catch. At this point all of the bits are read-only, so I'll drop the write to register 0x42. -- To view, visit https://review.coreboot.org/c/coreboot/+/78227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25aae540ff2ffa3ec5b93ed9caa838b4e50048d2 Gerrit-Change-Number: 78227 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 18:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/pch: Mark static devices hidden
by Patrick Rudolph (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78230?usp=email ) Change subject: sb/intel/bd82x6x/pch: Mark static devices hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Not in the scope of this commit, but do things generally work if hot-pluggable PCIe devices are adde […] Technically when the system is in S3 PCIe devices are cold plugged. I would assume it works fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/78230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a Gerrit-Change-Number: 78230 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 17:26:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/vboot: Fix the PSP verstage timestamps
by Karthik Ramasubramanian (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78231?usp=email ) Change subject: soc/amd/common/vboot: Fix the PSP verstage timestamps ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/vboot/vboot_bootblock.c: https://review.coreboot.org/c/coreboot/+/78231/comment/a9cf5944_087a4d7b : PS1, Line 48: * We ignore the time between x86 processor release and bootblock. : * Since timestamp_add subtracts base_time, we first add old base_time : * to make it absolute then add base_timestamp again since : * it'll be a new base_time. > It looks like this needs to be updated to describe why `tse->entry_stamp` is added also. Actually this comment already is saying that base_time is added to entry_timestamp to make it absolute. Conversion comment is coming after that. So I think the comment itself does not need update. -- To view, visit https://review.coreboot.org/c/coreboot/+/78231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e52bef22f65596152f29c511bed680427660ff5 Gerrit-Change-Number: 78231 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 17:11:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Martin Roth, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78232?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ce75b762bda90a5fa3bc546de42bc5d55637e17 Gerrit-Change-Number: 78232 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 17:04:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: vendorcode/amd: Add opensil code
by Martin L Roth (Code Review) 04 Oct '23

04 Oct '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76510?usp=email ) Change subject: vendorcode/amd: Add opensil code ...................................................................... Abandoned Replaced by a submodule -- To view, visit https://review.coreboot.org/c/coreboot/+/76510?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39057cf122aacd319deb6f43f165274f6535cc9b Gerrit-Change-Number: 76510 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit October 2023