coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[XS] Change in coreboot[main]: Enable split cse firmware sync on rex
by Krishna P Bhat D (Code Review) 05 Oct '23

05 Oct '23

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75522?usp=email ) Change subject: Enable split cse firmware sync on rex ...................................................................... Abandoned Alternate implementation got merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/75522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f254e014e4bcada2eccab169f61b415c23415ae Gerrit-Change-Number: 75522 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[main]: mtl: Allow call to cse_fw_sync() in romstage with defer CSE downgrade...
by Krishna P Bhat D (Code Review) 05 Oct '23

05 Oct '23

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76114?usp=email ) Change subject: mtl: Allow call to cse_fw_sync() in romstage with defer CSE downgrade config ...................................................................... Abandoned Alternate implementation got merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/76114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie84c70bb317a7c426f1a6281bff6f86da255bf19 Gerrit-Change-Number: 76114 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[main]: [DO_NOT_MERGE] Disable Vt-d
by Ravishankar Sarawadi (Code Review) 05 Oct '23

05 Oct '23

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78248?usp=email ) Change subject: [DO_NOT_MERGE] Disable Vt-d ...................................................................... [DO_NOT_MERGE] Disable Vt-d Change-Id: Ib7a4087423411ff9473954c4b1c75814bfc098c7 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/78248/1 diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 40b7c47..a3725d9 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -300,7 +300,7 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { - m_cfg->VtdDisable = 0; + m_cfg->VtdDisable = 1; m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/78248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7a4087423411ff9473954c4b1c75814bfc098c7 Gerrit-Change-Number: 78248 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: cse: Add a config option to defer FW downgrade to post FSP-M in romstage
by Krishna P Bhat D (Code Review) 05 Oct '23

05 Oct '23

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76112?usp=email ) Change subject: cse: Add a config option to defer FW downgrade to post FSP-M in romstage ...................................................................... Abandoned Alternate implementation got merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/76112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If11f8cd071803bcf85f4f3e84e13c5acbb49ffad Gerrit-Change-Number: 76112 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[M] Change in coreboot[main]: cse: Add deferred CSE downgrade flow
by Krishna P Bhat D (Code Review) 05 Oct '23

05 Oct '23

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/76113?usp=email ) Change subject: cse: Add deferred CSE downgrade flow ...................................................................... Abandoned Alternate implementation got merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/76113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d72de9e1d20219ebecc8c9c60ced77fca568543 Gerrit-Change-Number: 76113 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[main]: common/block/cse: Add config to split CSE firmware sync
by Krishna P Bhat D (Code Review) 05 Oct '23

05 Oct '23

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75514?usp=email ) Change subject: common/block/cse: Add config to split CSE firmware sync ...................................................................... Abandoned Alternate implementation got merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/75514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb984dedf44c25dcd0760b618d6c1e5de13d75c3 Gerrit-Change-Number: 75514 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: abandon

1 0

[L] Change in coreboot[master]: mb/google/dedede: Create dexi variant
by Kenneth Chan (Code Review) 05 Oct '23

05 Oct '23

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78247?usp=email ) Change subject: mb/google/dedede: Create dexi variant ...................................................................... mb/google/dedede: Create dexi variant Create the dexi variant of the taranza reference project by copying the files to a new directory named for the variant. BUG=b:303533815 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DEXI Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I513bc8e44ceb64c9f22a136a512ceb6ce1ff45a3 --- A src/mainboard/google/dedede/variants/dexi/Makefile.inc A src/mainboard/google/dedede/variants/dexi/gpio.c A src/mainboard/google/dedede/variants/dexi/include/variant/ec.h A src/mainboard/google/dedede/variants/dexi/include/variant/gpio.h A src/mainboard/google/dedede/variants/dexi/memory/Makefile.inc A src/mainboard/google/dedede/variants/dexi/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/dexi/overridetree.cb A src/mainboard/google/dedede/variants/dexi/ramstage.c A src/mainboard/google/dedede/variants/dexi/variant.c 10 files changed, 495 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/78247/1 diff --git a/src/mainboard/google/dedede/variants/dexi/Makefile.inc b/src/mainboard/google/dedede/variants/dexi/Makefile.inc new file mode 100644 index 0000000..c4bbd20 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c + +ramstage-y += variant.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/dedede/variants/dexi/gpio.c b/src/mainboard/google/dedede/variants/dexi/gpio.c new file mode 100644 index 0000000..89a7a77 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/gpio.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + /* A12 : USB_OC1_N */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : USB_OC2_N */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : USB_OC3_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A18 : USB_OC0_N */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* B9 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D4 : LAN_PE_ISOLATE_ODL_R */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* D17 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + + /* E13 : GPP_E13/DDI0_DDC_SCL */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14 : GPP_E14/DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : GPP_E15/DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + /* E16 : GPP_E16/DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* H15 : I2S_SPK_BCLK */ + PAD_NC(GPP_H15, NONE), + + /* R6 : I2S_SPK_LRCK */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_SPK_AUDIO */ + PAD_NC(GPP_R7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), + /* S6 : DMIC0_CLK */ + PAD_NC(GPP_S6, NONE), + /* S7 : DMIC0_DATA */ + PAD_NC(GPP_S7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/dexi/include/variant/ec.h b/src/mainboard/google/dedede/variants/dexi/include/variant/ec.h new file mode 100644 index 0000000..039e46b --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/dibbi/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/dexi/include/variant/gpio.h b/src/mainboard/google/dedede/variants/dexi/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/dexi/memory/Makefile.inc b/src/mainboard/google/dedede/variants/dexi/memory/Makefile.inc new file mode 100644 index 0000000..121eea2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dexi/memory/ src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/dedede/variants/dexi/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/dexi/memory/dram_id.generated.txt new file mode 100644 index 0000000..947e7ca --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/memory/dram_id.generated.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dexi/memory/ src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H54G46CYRBX267 0 (0000) +H54G56CYRBX247 1 (0001) +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) diff --git a/src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt new file mode 100644 index 0000000..99a1412 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H54G46CYRBX267 +H54G56CYRBX247 +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/dedede/variants/dexi/overridetree.cb b/src/mainboard/google/dedede/variants/dexi/overridetree.cb new file mode 100644 index 0000000..fc80ba2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/overridetree.cb @@ -0,0 +1,304 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[4] = { + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + }" + + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + # Enable Root Port 3 (index 2) for LAN + # External PCIe port 7 is mapped to PCIe Root Port 3 + register "PcieRpEnable[2]" = "1" + register "PcieClkSrcUsage[4]" = "2" + + # Enable Root Port 7 (index 6) for WLAN + # External PCIe port 3 is mapped to PCIe Root Port 7 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + + # Disable PCIe Root Port 8 + register "PcieRpEnable[7]" = "0" + + # Audio related configurations + register "PchHdaAudioLinkDmicEnable[0]" = "0" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + + # Disable SD card + register "sdcard_cd_gpio" = "0" + register "SdCardPowerEnableActiveHigh" = "0" + + # Disable eDP on port A + register "DdiPortAConfig" = "0" + + # Enable HPD and DDC for DDI port A + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "1" + + # Does not support external vnn power rail + register "disable_external_bypass_vr" = "1" + + # USB Port Configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A0 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A1 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A2 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A3 + register "usb2_ports[6]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A4 + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(7)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN) + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 100, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Power"" + register "options.tsr[2].desc" = ""Chassis"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 3)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A4"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C 4 + device pci 1c.2 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW0_03" # GPP_B3 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + register "device_index" = "0" + device pci 00.0 on end + end + end # PCI Express Root Port 3 - RTL8111H LAN + device pci 1c.6 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 7 - WLAN + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1f.3 on end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/dexi/ramstage.c b/src/mainboard/google/dedede/variants/dexi/ramstage.c new file mode 100644 index 0000000..afb3fc7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/ramstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +/* + * Psys_pmax considerations + * + * Given the hardware design in taranza, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638) + * R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000, + .bj_power_w = 65, +}; + +void variant_devtree_update(void) +{ + variant_update_psys_power_limits(&psys_config); +} diff --git a/src/mainboard/google/dedede/variants/dexi/variant.c b/src/mainboard/google/dedede/variants/dexi/variant.c new file mode 100644 index 0000000..c0a66fa --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar-taranza.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I513bc8e44ceb64c9f22a136a512ceb6ce1ff45a3 Gerrit-Change-Number: 78247 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/quandiso: Fix touchscreen probed flag
by Robert Chen (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Derek Huang, Eric Lai, Martin L Roth, Nick Vaccaro, Reka Norman, Shawn Ku, Subrata Banik. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78167?usp=email ) Change subject: mb/google/nissa/var/quandiso: Fix touchscreen probed flag ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78167/comment/09466ab7_cb86fa0e : PS1, Line 9: detect flag isn't ready in firmware-nissa-15217.B > Are you sure? Some nissa variants use detect flags in nissa firmware branch already. chromium:4769662 do not cherry-pick to firmware branch yet. I used the firmware branch build firmware on quandiso board and it did not work. Patchset: PS1: > If this is true, should we do for all nissa boards? No, this CL is for quandiso detected flag change on firmware branch too early. -- To view, visit https://review.coreboot.org/c/coreboot/+/78167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I674b636e1c5d8554ba91d380c61d381d7db95054 Gerrit-Change-Number: 78167 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Derek Huang <derekhuang(a)google.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shawn Ku <shawnku(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Oct 2023 02:19:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing
by Yidi Lin (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Hung-Te Lin, cong yang. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78185?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78185/comment/b96c7099_25b2fc6f : PS7, Line 16: BUG=b:302212730 BRANCH=corsola -- To view, visit https://review.coreboot.org/c/coreboot/+/78185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Gerrit-Change-Number: 78185 Gerrit-PatchSet: 7 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 01:18:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing
by cong yang (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Hung-Te Lin. cong yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78185?usp=email ) Change subject: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78185/comment/b694af96_2c7617a1 : PS6, Line 10: power ic > Power IC Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Gerrit-Change-Number: 78185 Gerrit-PatchSet: 7 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Oct 2023 00:37:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023