coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing
by cong yang (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Hung-Te Lin, cong yang. Hello Hung-Te Lin, Paul Menzel, Ruihai Zhou, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78185?usp=email to look at the new patch set (#7). Change subject: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing ...................................................................... mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing Based on the power sequence of the panel [1], the power on T3 sequence VSN to RESET should be larger than 1ms. Because the Power IC descending slope takes 2ms, actual measurement needs 3ms to meet the timing of panel sequence. [1] HX83102-J02_Datasheet_v03.pdf BUG=b:302212730 TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/panel_starmie.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78185/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Gerrit-Change-Number: 78185 Gerrit-PatchSet: 7 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/phoenix/psp_verstage: Fix the hash file names
by Karthik Ramasubramanian (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78236?usp=email ) Change subject: soc/amd/phoenix/psp_verstage: Fix the hash file names ...................................................................... soc/amd/phoenix/psp_verstage: Fix the hash file names Fix the hash file names to be used to verify signed PSP binaries when booting with VBOOT FW Slot B. BUG=None TEST=Build and boot to OS in Myst with PSP Verstage enabled using both VBOOT slots A and B. Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/phoenix/psp_verstage/chipset.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/78236/1 diff --git a/src/soc/amd/phoenix/psp_verstage/chipset.c b/src/soc/amd/phoenix/psp_verstage/chipset.c index cf03272..b7efdc9 100644 --- a/src/soc/amd/phoenix/psp_verstage/chipset.c +++ b/src/soc/amd/phoenix/psp_verstage/chipset.c @@ -140,11 +140,11 @@ PSP_FW_HASH_FILE_NAME("a", "2")); } else { update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_STAGE1, - PSP_FW_HASH_FILE_NAME("a", "")); + PSP_FW_HASH_FILE_NAME("b", "")); update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_STAGE2, - PSP_FW_HASH_FILE_NAME("a", "1")); + PSP_FW_HASH_FILE_NAME("b", "1")); update_one_psp_fw_hash_table(CMD_SET_FW_HASH_TABLE_TOS, - PSP_FW_HASH_FILE_NAME("a", "2")); + PSP_FW_HASH_FILE_NAME("b", "2")); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/78236?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0 Gerrit-Change-Number: 78236 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/myst: Enable CBFS Verification
by Karthik Ramasubramanian (Code Review) 05 Oct '23

05 Oct '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78235?usp=email ) Change subject: mb/google/myst: Enable CBFS Verification ...................................................................... mb/google/myst: Enable CBFS Verification Enable RO verification by GSC and RO/RW CBFS verification. BUG=b:277087492 TEST=Build and boot to OS in Myst with CBFS verification enabled using PSP verstage. Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/myst/Kconfig 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/78235/1 diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index fbb3687..70986f8 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -88,11 +88,6 @@ bool default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK -# TODO(b/277087492): Enable GSC CBFS verification -config VBOOT_GSCVD - bool - default n - # Override PSP_SOFTFUSE_BITS from soc/amd/phoenix. # The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA). config PSP_SOFTFUSE_BITS -- To view, visit https://review.coreboot.org/c/coreboot/+/78235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad Gerrit-Change-Number: 78235 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/phoenix: Disable CCP DMA in PSP Verstage
by Karthik Ramasubramanian (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78234?usp=email ) Change subject: soc/amd/phoenix: Disable CCP DMA in PSP Verstage ...................................................................... soc/amd/phoenix: Disable CCP DMA in PSP Verstage Some stalls are observed while using CCP DMA in PSP verstage - especially with CBFS verification enabled. Also with RW CBFS verification enabled, the entire firmware body is not loaded during verstage for verification. Instead the files are verified as and when they are loaded from CBFS. Hence the impact to boot time is reduced since only few files are loaded during PSP verstage. Hence disable CCP DMA in PSP verstage until the root cause is identified. BUG=None TEST=Build and boot to OS in Myst with CBFS verification enabled. Change-Id: I22ac108b08abcfe432dfd175644393e384888e11 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/phoenix/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/78234/1 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index ec1a9e9..c9aa32c 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -25,7 +25,8 @@ select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK - select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK + # TODO: (b/303516266) Re-enable CCP DMA after addressing a stall + # select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/78234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22ac108b08abcfe432dfd175644393e384888e11 Gerrit-Change-Number: 78234 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/phoenix: Add build rules to enable CBFS verification
by Karthik Ramasubramanian (Code Review) 05 Oct '23

05 Oct '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78233?usp=email ) Change subject: soc/amd/phoenix: Add build rules to enable CBFS verification ...................................................................... soc/amd/phoenix: Add build rules to enable CBFS verification Add SPI flash RO ranges to be verified by GSC in order to enable CBFS verification. Also with CBFS verification enabled, CBFS metadata is more than 64 bytes. So configure the offset of amdfw_a/b to 128 bytes - next address aligned to 64 bytes. BUG=b:277087492 TEST=Build and boot to OS in Myst with and without CBFS verification enabled. Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/phoenix/Makefile.inc 1 file changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78233/1 diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index d589bf1..ee7ccea 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -46,9 +46,9 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common -# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes +# 0x80 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough -AMD_FW_AB_POSITION := 0x40 +AMD_FW_AB_POSITION := 0x80 PHOENIX_FW_A_POSITION=$(call int-add, \ $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) @@ -337,4 +337,17 @@ endif # CONFIG_SEPARATE_SIGNED_PSPFW endif +# Add ranges for all components up until the first segment of BIOS to be verified by GSC +ifeq ($(CONFIG_VBOOT_GSCVD),y) +# Adding range for Bootblock +vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62) +# Adding range for PSP Stage1 Bootloader +vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01) + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# Adding range for PSP Verstage +vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52) +endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) + endif # ($(CONFIG_SOC_AMD_PHOENIX),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/78233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347 Gerrit-Change-Number: 78233 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/mtl: Load eDP PHY firmware for early graphics support
by Anil Kumar K (Code Review) 04 Oct '23

04 Oct '23

Anil Kumar K has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77543?usp=email ) Change subject: soc/intel/mtl: Load eDP PHY firmware for early graphics support ...................................................................... Abandoned not required as these calls are being made from FSP code -- To view, visit https://review.coreboot.org/c/coreboot/+/77543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ccc294784b2879e601d92040c8c3b0e1f4bf024 Gerrit-Change-Number: 77543 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: soc/intel/cmn/cse: Add support for BUP_COMMON_LOAD_EDP_PHY command
by Anil Kumar K (Code Review) 04 Oct '23

04 Oct '23

Anil Kumar K has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77110?usp=email ) Change subject: soc/intel/cmn/cse: Add support for BUP_COMMON_LOAD_EDP_PHY command ...................................................................... Abandoned not required as these calls are being made from FSP code -- To view, visit https://review.coreboot.org/c/coreboot/+/77110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia18b895b2b4247266140670024cc0d27852efe42 Gerrit-Change-Number: 77110 Gerrit-PatchSet: 8 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: vendorcode/intel: Add StatusCodeDataTypeDebug.h
by Jérémy Compostella (Code Review) 04 Oct '23

04 Oct '23

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77228?usp=email ) Change subject: vendorcode/intel: Add StatusCodeDataTypeDebug.h ...................................................................... Abandoned uGOP solution has rejected. -- To view, visit https://review.coreboot.org/c/coreboot/+/77228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idab0139ff0313372e211f679e6e799e2b29781fa Gerrit-Change-Number: 77228 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: soc/intel/meteorlake: Inform user of memory training and CSME update
by Jérémy Compostella (Code Review) 04 Oct '23

04 Oct '23

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77232?usp=email ) Change subject: soc/intel/meteorlake: Inform user of memory training and CSME update ...................................................................... Abandoned uGOP solution has rejected. -- To view, visit https://review.coreboot.org/c/coreboot/+/77232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I358b54c71533f3b905b68d7ac0710d2337ce451d Gerrit-Change-Number: 77232 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[L] Change in coreboot[main]: vendorcode/intel: Add uGOP support
by Jérémy Compostella (Code Review) 04 Oct '23

04 Oct '23

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77231?usp=email ) Change subject: vendorcode/intel: Add uGOP support ...................................................................... Abandoned uGOP solution has rejected. -- To view, visit https://review.coreboot.org/c/coreboot/+/77231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66ae5f1948474330bfa41c42cda7cc0738f7b9cd Gerrit-Change-Number: 77231 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit October 2023