coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Matt DeVillier (Code Review) 04 Oct '23

04 Oct '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78232?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Update amd_blobs submodule to upstream main branch Updating from commit id ae822f2d0db7 (2023-09-21): MDN: Restore SMU fw version 90.41.0 to commit id b1741d184add (2023-10-04): PCO: Update SMU firmware to 4.30.77.200 This brings in 1 new commit: b1741d184a PCO: Update SMU firmware to 4.30.77.200 BRANCH=zork BUG=b:299603947 Change-Id: I0ce75b762bda90a5fa3bc546de42bc5d55637e17 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/78232/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index ae822f2..b1741d1 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit ae822f2d0db7e9f9c8dff4ad1539ea2282f28f27 +Subproject commit b1741d184add2a38c5e8ff025593d0c1c48f782f -- To view, visit https://review.coreboot.org/c/coreboot/+/78232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ce75b762bda90a5fa3bc546de42bc5d55637e17 Gerrit-Change-Number: 78232 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/common/vboot: Fix the PSP verstage timestamps
by Jon Murphy (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, Martin Roth, Matt DeVillier. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78231?usp=email ) Change subject: soc/amd/common/vboot: Fix the PSP verstage timestamps ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e52bef22f65596152f29c511bed680427660ff5 Gerrit-Change-Number: 78231 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Oct 2023 16:17:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cse: Add API to check if CSE Firmware update is required
by Anil Kumar K (Code Review) 04 Oct '23

04 Oct '23

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78243?usp=email ) Change subject: soc/intel/cse: Add API to check if CSE Firmware update is required ...................................................................... soc/intel/cse: Add API to check if CSE Firmware update is required This patch adds a function to check if a CSE FW update is required during this boot. The function is expected to be used during use cases like Pre-Memory Sign of Life text display to inform user of a CSE Firmware update . Bug=279173035 TEST=build and boot on google/rex board. Call the function in romstage and confirm it returns True during CSE FW update and False otherwise Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: If5fae95786d28d586566881bc4436812754636ae --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/78243/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index bd06bbf..f03b1c6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1177,6 +1177,36 @@ backup_psr_data(); } +/* + * Check if a CSE Firmware update is required + * returns true if an update is required, false otherwise + */ +bool is_cse_fw_update_required(void) +{ + struct fw_version cbfs_rw_version; + int ret; + + if (!is_cse_fw_update_enabled()) + return false; + + /* + * First check if cse_bp_info_rsp global structure is populated + * else, this implies that cse_fill_bp_info() function is not called + */ + if (!is_cse_bp_info_valid(&cse_bp_info_rsp)) + return false; + + if (get_cse_ver_from_cbfs(&cbfs_rw_version) == CB_ERR) + return false; + + ret = cse_compare_sub_part_version(&cbfs_rw_version, cse_get_rw_version()); + if (ret == 0) + /* return false if CSE FW update is not required */ + return false; + else + return true; +} + static uint8_t cse_fw_update(void) { struct region_device target_rdev; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f84dba8..3db1324 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -611,4 +611,9 @@ /* Fills the CSE Boot Partition Info response */ void cse_fill_bp_info(void); +/* + * Check if a CSE Firmware update is required + * Returns true if an update is required, false otherwise + */ +bool is_cse_fw_update_required(void); #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/78243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5fae95786d28d586566881bc4436812754636ae Gerrit-Change-Number: 78243 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/genoa: Enable uart
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76507?usp=email ) Change subject: soc/amd/genoa: Enable uart ...................................................................... Patch Set 7: (1 comment) File src/mainboard/amd/onyx/Kconfig: https://review.coreboot.org/c/coreboot/+/76507/comment/44238743_e14272cf : PS7, Line 1: if BOARD_AMD_ONYX can this file be moved to a separate commit from the genoa code? -- To view, visit https://review.coreboot.org/c/coreboot/+/76507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Gerrit-Change-Number: 76507 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:37:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/genoa: add GPIO support
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78222?usp=email ) Change subject: soc/amd/genoa: add GPIO support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Gerrit-Change-Number: 78222 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:35:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: Add SMI support
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78221?usp=email ) Change subject: soc/amd/genoa: Add SMI support ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/genoa/include/soc/smi.h: https://review.coreboot.org/c/coreboot/+/78221/comment/2d52232c_b0e820bb : PS1, Line 8: /* @Todo: Update the SMI details for Genoa */ Any reason this is left as a TODO instead of doing it before the patch is submitted? -- To view, visit https://review.coreboot.org/c/coreboot/+/78221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Gerrit-Change-Number: 78221 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:34:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/amd/genoa: add GPIO definitions
by Martin Roth (Code Review) 04 Oct '23

04 Oct '23

Attention is currently required from: Varshit Pandya. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78220?usp=email ) Change subject: soc/amd/genoa: add GPIO definitions ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/genoa/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/78220/comment/582d9cda_4b2e84ce : PS1, Line 6: /* @Todo: Updated GPIO device name for Genoa */ Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/78220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Gerrit-Change-Number: 78220 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Oct 2023 15:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78144?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug ...................................................................... mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: Derek Huang: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index c45d8f6..5c3e90c 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -82,6 +82,16 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + #Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/78144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Gerrit-Change-Number: 78144 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/dedede/var/taranza: Enable wake on USB2/3 (un)plug
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78068?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/taranza: Enable wake on USB2/3 (un)plug ...................................................................... mb/google/dedede/var/taranza: Enable wake on USB2/3 (un)plug Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. The physical USB slot is 6, USB2 port5 for Bluetooth, total USB2 port num is 7, USB3 keep 6. BUG=b:300844110 TEST=Verify USB-A device could wake up Taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78068 Reviewed-by: Ricky Chang <rickytlchang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/dedede/variants/taranza/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: Ricky Chang: Looks good to me, but someone else must approve Reka Norman: Looks good to me, approved build bot (Jenkins): Verified Sheng-Liang Pan: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb index 3b2f693..fc80ba2 100644 --- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb +++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb @@ -123,6 +123,20 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(7)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/78068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464 Gerrit-Change-Number: 78068 Gerrit-PatchSet: 5 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/jasperlake: Enable wake from USB
by Felix Held (Code Review) 04 Oct '23

04 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78086?usp=email ) Change subject: soc/intel/jasperlake: Enable wake from USB ...................................................................... soc/intel/jasperlake: Enable wake from USB Use the common UWES ACPI method to enable wake from USB. The only difference to other SoCs is that JSL only has 8 USB2 ports, so the USB3 PORTSC register offset is different. BUG=b:300844110 TEST=When enabled on taranza, all USB2 and USB3 ports can wake from suspend Change-Id: Ibc90246965d5d809123e954847543d28d78498a5 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78086 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> --- M src/soc/intel/jasperlake/acpi/xhci.asl M src/soc/intel/jasperlake/chip.h 2 files changed, 24 insertions(+), 0 deletions(-) Approvals: Sheng-Liang Pan: Looks good to me, but someone else must approve build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl index 8ecbe47..acaf450 100644 --- a/src/soc/intel/jasperlake/acpi/xhci.asl +++ b/src/soc/intel/jasperlake/acpi/xhci.asl @@ -2,6 +2,15 @@ #include <soc/gpe.h> +/* + * JSL has 8 USB2 ports, so the USB3 PORTSC registers start at + * 0x480 + 8 * 0x10 = 0x500 + */ +#define JSL_PORTSCXUSB3_OFFSET 0x500 + +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl> + /* XHCI Controller 0:14.0 */ Device (XHCI) @@ -10,6 +19,20 @@ Name (_PRW, Package () { GPE0_PME_B0, 3 }) + OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + Field (XPRT, AnyAcc, NoLock, Preserve) + { + Offset (0x10), + , 16, + XMEM, 16, /* MEM_BASE */ + } + + Method (_DSW, 3) + { + UWES ((\U2WE & 0xFF), PORTSCN_OFFSET, XMEM) + UWES ((\U3WE & 0x3F ), JSL_PORTSCXUSB3_OFFSET, XMEM) + } + Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 2af85e3..66ad223 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -11,6 +11,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/power_limit.h> +#include <intelblocks/xhci.h> #include <soc/gpe.h> #include <soc/pch.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/78086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc90246965d5d809123e954847543d28d78498a5 Gerrit-Change-Number: 78086 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit October 2023