coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly
by Kane Chen (Code Review) 05 Oct '23

05 Oct '23

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78252?usp=email ) Change subject: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly ...................................................................... soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly The original code only reserves IOM mmio, but there is other asl code requires to program ioe p2sb mmio such as IOE PCIE clk request control. See \_SB.ECLK.CLKD insrc/soc/intel/common/acpi/pcie_clk.asl TEST=suspend_stress_test 50 cycle pass, type-c display OK on screebo Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/meteorlake/p2sb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/78252/1 diff --git a/src/soc/intel/meteorlake/p2sb.c b/src/soc/intel/meteorlake/p2sb.c index ae9b9a4..761bb26 100644 --- a/src/soc/intel/meteorlake/p2sb.c +++ b/src/soc/intel/meteorlake/p2sb.c @@ -35,7 +35,7 @@ static void ioe_p2sb_read_resources(struct device *dev) { /* Add the fixed MMIO resource for IOM */ - mmio_range(dev, PCI_BASE_ADDRESS_0, IOM_BASE_ADDR, IOM_BASE_SIZE); + mmio_range(dev, PCI_BASE_ADDRESS_0, IOE_P2SB_BAR, IOE_P2SB_SIZE); } static void p2sb_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/78252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Gerrit-Change-Number: 78252 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly
by Kane Chen (Code Review) 05 Oct '23

05 Oct '23

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78251?usp=email ) Change subject: soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly ...................................................................... soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly The original code only reserves IOM mmio, but there is other asl code requires to program ioe p2sb mmio such as IOE PCIE clk request control. See \_SB.ECLK.CLKD insrc/soc/intel/common/acpi/pcie_clk.asl TEST=suspend_stress_test 50 cycle pass, type-c display OK Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/meteorlake/p2sb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/78251/1 diff --git a/src/soc/intel/meteorlake/p2sb.c b/src/soc/intel/meteorlake/p2sb.c index ae9b9a4..761bb26 100644 --- a/src/soc/intel/meteorlake/p2sb.c +++ b/src/soc/intel/meteorlake/p2sb.c @@ -35,7 +35,7 @@ static void ioe_p2sb_read_resources(struct device *dev) { /* Add the fixed MMIO resource for IOM */ - mmio_range(dev, PCI_BASE_ADDRESS_0, IOM_BASE_ADDR, IOM_BASE_SIZE); + mmio_range(dev, PCI_BASE_ADDRESS_0, IOE_P2SB_BAR, IOE_P2SB_SIZE); } static void p2sb_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/78251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Gerrit-Change-Number: 78251 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Disable package C-state auto demotion for rex &...
by Sukumar Ghorai (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Hello Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78250?usp=email to look at the new patch set (#2). Change subject: mb/google/{rex,ovis}: Disable package C-state auto demotion for rex & ovis ...................................................................... mb/google/{rex,ovis}: Disable package C-state auto demotion for rex & ovis Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 4 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/78250/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Gerrit-Change-Number: 78250 Gerrit-PatchSet: 2 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Disable package C-state auto demotion for rex &...
by Sukumar Ghorai (Code Review) 05 Oct '23

05 Oct '23

Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78250?usp=email ) Change subject: mb/google/{rex,ovis}: Disable package C-state auto demotion for rex & ovis ...................................................................... mb/google/{rex,ovis}: Disable package C-state auto demotion for rex & ovis Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 4 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/78250/1 diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 6fc0dc0..7d39ece 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -36,6 +36,9 @@ # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" + # Disable PKGC-state demotion + register "disable_package_c_state_demotion" = "1" + # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index ec57ee7..5894fe6 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -36,6 +36,9 @@ # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" + # Disable PKGC-state demotion + register "disable_package_c_state_demotion" = "1" + # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index ec38e80..6210406 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -419,6 +419,8 @@ * Enable or Disable Package C-state Demotion. * Default is set to 0. * Set this to 1 in order to disable Package C-state demotion. + * NOTE: Un-Demotion from demoted Package C-state needs to be disabled + * when auto demotion is disabled. */ bool disable_package_c_state_demotion; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 5350783..5ec9cf4 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -666,6 +666,7 @@ s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion; s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; + s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion; s_cfg->PmcV1p05PhyExtFetControlEn = 1; /* Enable PCH to CPU energy report feature. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Gerrit-Change-Number: 78250 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Follow PCH BIOS spec
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Hello Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78225?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Kyösti Mälkki, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: sb/intel/bd82x6x: Follow PCH BIOS spec ...................................................................... sb/intel/bd82x6x: Follow PCH BIOS spec PCH BIOS spec says that BIOS must clear BIT26 in register 0x338 in PEI, as done on lynxpoint. Copy and adapt the lynxpoint code to do the same on bd82x6x. Add special case for UM77 chipset, which only has 4 PCIe ports. Test: System still boots and all PCIe ports are fully working. Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/78225/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Gerrit-Change-Number: 78225 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email ) Change subject: sb/intel/bd82x6x: Improve SLCAP ...................................................................... Patch Set 2: (2 comments) File src/southbridge/intel/bd82x6x/pch.h: https://review.coreboot.org/c/coreboot/+/78228/comment/4aa13251_548ab464 : PS1, Line 90: #define D28Fx_SLCAP 0x54 > ``` […] Done File src/southbridge/intel/bd82x6x/pcie.c: https://review.coreboot.org/c/coreboot/+/78228/comment/7782f112_70061d31 : PS1, Line 141: reg32 = pci_read_config32(dev, D28Fx_SLCAP); > Probably should utilise and extend ones from pci_def.h here. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Gerrit-Change-Number: 78228 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 06:16:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Use helper for PCIe hotplug
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78227?usp=email ) Change subject: sb/intel/bd82x6x: Use helper for PCIe hotplug ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/bd82x6x/pcie.c: https://review.coreboot.org/c/coreboot/+/78227/comment/9db83cf1_1f0f880a : PS1, Line 213: pci_write_config16(dev, 0x42, 0x142); > Good catch. At this point all of the bits are read-only, so I'll drop the write to register 0x42. See CB:78238 -- To view, visit https://review.coreboot.org/c/coreboot/+/78227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25aae540ff2ffa3ec5b93ed9caa838b4e50048d2 Gerrit-Change-Number: 78227 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 06:16:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Disable unused PCIe root ports
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78226?usp=email ) Change subject: sb/intel/bd82x6x: Disable unused PCIe root ports ...................................................................... Patch Set 2: (3 comments) File src/southbridge/intel/bd82x6x/pch.h: https://review.coreboot.org/c/coreboot/+/78226/comment/bd06069b_9b3b7df0 : PS1, Line 86: #define D28Fx_XCAP 0x42 > I believe these are offsets into PCI express capability block at 0x40 + PCI_EXP_xxx from pci_def.h? […] Done https://review.coreboot.org/c/coreboot/+/78226/comment/b484e048_6e37c0f0 : PS1, Line 88: #define D28Fx_LCTL 0x50 > ``` […] Done https://review.coreboot.org/c/coreboot/+/78226/comment/c582be60_b8e9a574 : PS1, Line 90: #define D28Fx_SLSTS 0x58 > Seems like 0x58 would be CTL, 0x5A and 0x5B status? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Gerrit-Change-Number: 78226 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 06:15:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Only use supported C-states
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Kyösti Mälkki, Paul Menzel. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78194?usp=email ) Change subject: cpu/intel/model_206ax: Only use supported C-states ...................................................................... Patch Set 4: (1 comment) File src/cpu/intel/model_206ax/acpi.c: https://review.coreboot.org/c/coreboot/+/78194/comment/596b5b3b_4a90198b : PS3, Line 160: count, c_state_names[acpi_cstates[i]]); > Should the logge ACPI C%d here use the .ctype field value? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Gerrit-Change-Number: 78194 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Oct 2023 06:15:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Print supported C-states
by Patrick Rudolph (Code Review) 05 Oct '23

05 Oct '23

Attention is currently required from: Felix Held, Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78133?usp=email ) Change subject: cpu/intel/model_206ax: Print supported C-states ...................................................................... Patch Set 7: (1 comment) File src/cpu/intel/model_206ax/acpi.c: https://review.coreboot.org/c/coreboot/+/78133/comment/1b617ca6_65406c1a : PS5, Line 128: print_supported_cstates(); > Sounds good. Will do on the next push. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Gerrit-Change-Number: 78133 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 05 Oct 2023 06:15:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2023