coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yidi Lin (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Julius Werner, Nico Huber, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 16: (1 comment) File 3rdparty/amd_blobs: PS15: > Submodule changes are unrelated. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:59:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yidi Lin (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Julius Werner, Nico Huber, Paul Menzel, Yidi Lin. Yidi Lin has uploaded a new patch set (#16) to the change originally created by Jianjun Wang. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... soc/mediatek: PCI: Fix translation window Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 58 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yu-Ping Wu (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Julius Werner, Nico Huber, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 15: (1 comment) File 3rdparty/amd_blobs: PS15: Submodule changes are unrelated. -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:51:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Subrata Banik (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Paul Menzel, Ravishankar Sarawadi, Tarun, Utkarsh H Patel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 7: Code-Review+2 (1 comment) File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/78163/comment/e2f547c1_1b33156e : PS6, Line 3: 0xC00 > Added based on config. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 7 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:43:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/karis: Correct devicetree touchscreen settings
by Subrata Banik (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Lucas Chen, Ren Kuo, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78254?usp=email ) Change subject: mb/google/rex/var/karis: Correct devicetree touchscreen settings ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: the only difference is AP FW doing the init vs init at runtime using ACPI. -- To view, visit https://review.coreboot.org/c/coreboot/+/78254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Gerrit-Change-Number: 78254 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:42:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/karis: Correct devicetree touchscreen settings
by Subrata Banik (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Lucas Chen, Ren Kuo, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78254?usp=email ) Change subject: mb/google/rex/var/karis: Correct devicetree touchscreen settings ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Gerrit-Change-Number: 78254 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:41:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yidi Lin (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Julius Werner, Nico Huber, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 15: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/78044/comment/e3150a1c_0ac77c25 : PS14, Line 240: if (mtk_pcie_set_trans_window(&count, table_base, &conf->mmio_res_io) : < 0) { : printk(BIOS_ERR, "%s: Failed to set IO window, ignore it\n", : __func__); : count = 0; : } : : /* Initialize memory resources constraints. */ : if (mtk_pcie_set_trans_window(&count, table_base, &conf->mmio_res_mem) : < 0) > Any update jianjun? done -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:38:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yidi Lin (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel, Yidi Lin, Yu-Ping Wu. Yidi Lin has uploaded a new patch set (#15) to the change originally created by Jianjun Wang. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... soc/mediatek: PCI: Fix translation window Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M 3rdparty/amd_blobs M 3rdparty/arm-trusted-firmware M 3rdparty/blobs M 3rdparty/fsp M 3rdparty/intel-microcode M 3rdparty/libgfxinit M 3rdparty/libhwbase M 3rdparty/qc_blobs M 3rdparty/vboot M src/soc/mediatek/common/pcie.c M util/goswid M util/nvidia/cbootimage 12 files changed, 69 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78044/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yu-Ping Wu (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Nico Huber, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 14: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/78044/comment/8df43840_16d882be : PS14, Line 240: if (mtk_pcie_set_trans_window(&count, table_base, &conf->mmio_res_io) : < 0) { : printk(BIOS_ERR, "%s: Failed to set IO window, ignore it\n", : __func__); : count = 0; : } : : /* Initialize memory resources constraints. */ : if (mtk_pcie_set_trans_window(&count, table_base, &conf->mmio_res_mem) : < 0) > Please fix it. Any update jianjun? -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 03:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing
by Yu-Ping Wu (Code Review) 06 Oct '23

06 Oct '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78185?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing ...................................................................... mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing Based on the power sequence of the panel [1], the power on T3 sequence VSN to RESET should be larger than 1ms. Because the Power IC descending slope takes 2ms, actual measurement needs 3ms to meet the timing of panel sequence. [1] HX83102-J02_Datasheet_v03.pdf BUG=b:302212730 BRANCH=corsola TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78185 Reviewed-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/panel_starmie.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Ruihai Zhou: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index c55d82d..55e9dbf 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -34,6 +34,7 @@ gpio_output(GPIO_EN_PP3300_DISP_X, 1); mdelay(2); gpio_output(GPIO_EN_PP3300_SDBRDG_X, 1); + mdelay(3); } else if (tps65132s_setup(&cfg) != CB_SUCCESS) { printk(BIOS_ERR, "Failed to setup tps65132s\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/78185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Gerrit-Change-Number: 78185 Gerrit-PatchSet: 9 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023