coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/rex/var/rex0: update dptf thermal settings to start fan ear...
by Sumeet R Pawnikar (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Eran Mitrani, Eric Lai, Eric Lai, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78180?usp=email ) Change subject: mb/google/rex/var/rex0: update dptf thermal settings to start fan earlier ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78180/comment/fc9c1c0c_1015ca46 : PS2, Line 7: update dptf thermal settings > Maybe more specific: […] Acknowledged https://review.coreboot.org/c/coreboot/+/78180/comment/70dfa7f2_19e12f5c : PS2, Line 9: During internal testing observed > Maybe: Internal testing showed, … Done https://review.coreboot.org/c/coreboot/+/78180/comment/c9fcbb35_ae333eb2 : PS2, Line 10: While this even fan does not start : to control the temperature. > Maybe: In this situation, the fan does not even start to lower the temperature. Done https://review.coreboot.org/c/coreboot/+/78180/comment/eaef3bbe_38c99767 : PS2, Line 12: high > too high Acknowledged https://review.coreboot.org/c/coreboot/+/78180/comment/f2b78663_8561a0a7 : PS2, Line 13: With updated new settings > Please document, where the new settings came from. […] Done https://review.coreboot.org/c/coreboot/+/78180/comment/416c6a5a_59fc41ab : PS2, Line 13: start fan early for TSR0 and TSR1 : sensors to prevent high CPU temperature > Maybe: … the fan starts early for TSR0 and TSR1 so the temperature stays below X °C. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6580652d6165946e98ecf1b46ace3352cd34dcdf Gerrit-Change-Number: 78180 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 05:23:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/var/rex0: update dptf thermal settings to start fan ear...
by Sumeet R Pawnikar (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Eran Mitrani, Eric Lai, Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun. Hello Eran Mitrani, Eric Lai, Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78180?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik Change subject: mb/google/rex/var/rex0: update dptf thermal settings to start fan earlier ...................................................................... mb/google/rex/var/rex0: update dptf thermal settings to start fan earlier Internal testing showed that CPU heatsink gets hot and temperature goes over 75C. In this situation, the fan does not even start to lower down CPU temperature. This is because of existing temperature thresholds of TSR0 and TSR1 sensors are set at 45C to start fan. With updated new settings based on tuning from thermal team, the fan starts early at 43C for TSR0 and TSR1 so the CPU temperature stays below 75C. BUG=b:302673874 TEST=Built and tested on google/rex board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Change-Id: I6580652d6165946e98ecf1b46ace3352cd34dcdf --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/78180/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6580652d6165946e98ecf1b46ace3352cd34dcdf Gerrit-Change-Number: 78180 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email ) Change subject: sb/intel/bd82x6x: Improve SLCAP ...................................................................... Patch Set 2: (1 comment) File src/southbridge/intel/bd82x6x/pcie.c: https://review.coreboot.org/c/coreboot/+/78228/comment/9422b864_7444f48c : PS2, Line 152: reg32 |= (slot_number++ << 19); > The SI Slot Implemented flag is now always set for enabled or hot pluggable ports, thus the check wo […] Yes, I left a request on another commit to leave a comment that we don't follow the specs when we unconditionally set (or do not clear) SI bit for upstream links of integrated devices. If the spec says SLTCAP must be implemented when SI is set, it implies it may not be implemented otherwise. I had a look at pciutils/lspci source, seemed like it does not parse or print SLTCAP when SI=0. I'd still like the first slot_number to be programmed with PSN=1 to make it unique from the SLTCAP registers that default to PSN=0 and are not programmed at all. -- To view, visit https://review.coreboot.org/c/coreboot/+/78228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Gerrit-Change-Number: 78228 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 05:04:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Follow PCH BIOS spec
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78225?usp=email ) Change subject: sb/intel/bd82x6x: Follow PCH BIOS spec ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Gerrit-Change-Number: 78225 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 04:32:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Only use supported C-states
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Patrick Rudolph, Paul Menzel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78194?usp=email ) Change subject: cpu/intel/model_206ax: Only use supported C-states ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/cpu/intel/model_206ax/acpi.c: https://review.coreboot.org/c/coreboot/+/78194/comment/2a02d726_5ef07a83 : PS4, Line 161: acpigen_write_CST_package(acpi_cstate_map, count); Just an idea for future.. if we create the exact same _CST for each thread, could we not replace it with a reference something like Return("\\\\CP00._CST") to reduce amount of ACPI table space? -- To view, visit https://review.coreboot.org/c/coreboot/+/78194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Gerrit-Change-Number: 78194 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 Oct 2023 04:29:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Print supported C-states
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Felix Held, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78133?usp=email ) Change subject: cpu/intel/model_206ax: Print supported C-states ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Gerrit-Change-Number: 78133 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 Oct 2023 04:17:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86/cpu_common: Add cpu_get_c_substate_support
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78224?usp=email ) Change subject: arch/x86/cpu_common: Add cpu_get_c_substate_support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie57e87609ea5d6ec6f37154e8b84f1e9574aa4a9 Gerrit-Change-Number: 78224 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 04:13:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/pch: Mark static devices hidden
by Kyösti Mälkki (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78230?usp=email ) Change subject: sb/intel/bd82x6x/pch: Mark static devices hidden ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > All hot-pluggable PCIe root bridges use pciexp_hotplug_scan_bridge() to reserve a secondary-side bus […] ACPI tables are not recreated on S3 resume path. So the cases where normal boot path has recorded any PCI bus numbers inside ACPI objects are potential failures. But as you noted, hot-plugable buses are now centrally managed such that the problem should not occur. -- To view, visit https://review.coreboot.org/c/coreboot/+/78230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a Gerrit-Change-Number: 78230 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 04:10:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/mediatek: PCI: Fix translation window
by Yu-Ping Wu (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Hung-Te Lin, Jianjun Wang, Julius Werner, Nico Huber, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78044?usp=email ) Change subject: soc/mediatek: PCI: Fix translation window ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Gerrit-Change-Number: 78044 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 04:04:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2023