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Hello Angel Pons, Kyösti Mälkki, Paul Menzel, build bot (Jenkins),
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Change subject: sb/intel/common/spi: Fix I/O alignment
......................................................................
sb/intel/common/spi: Fix I/O alignment
On ICH9 the SPI control register is not naturally aligned
and a word write might be split into smaller naturally aligned
I/O transactions.
As the first byte starts a new SPI transfer, replace the existing
word write with two byte writes and write the second byte first.
This is required for platforms that do not support unaligned
word I/O instructions and would start a SPI transfer while the
second byte hasn't reached the control register yet.
TEST: Virtual SPI controller on qemu 8.0 doesn't start a transfer
early.
Change-Id: Id05b1a080911b71b94ef781c6e26d98165f02f67
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/southbridge/intel/common/spi.c
1 file changed, 16 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/78090/2
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Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78249?usp=email )
Change subject: mb/google/dedede: Create dexi variant
......................................................................
Patch Set 4: Code-Review+1
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Hello Derek Huang, build bot (Jenkins),
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Change subject: mb/google/dedede/var/boxy: Add wait for HPD function
......................................................................
mb/google/dedede/var/boxy: Add wait for HPD function
Boxy project need to wait for HPD ready to continue boot in ramstage to
avoid no display in DEV screen and recovery screen
BUG=b:303346324
TEST=Both type-c ports can display in DEV screen and recovery screen
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9
---
M src/mainboard/google/dedede/mainboard.c
M src/mainboard/google/dedede/variants/boxy/ramstage.c
2 files changed, 48 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/78146/3
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Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78146?usp=email )
Change subject: mb/google/dedede/var/boxy: Add wait for HPD function
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/dedede/variants/boxy/ramstage.c:
https://review.coreboot.org/c/coreboot/+/78146/comment/48df3a4d_039c82ab :
PS1, Line 69: wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms);
> If only C1 or HDMI is connected, I think this will always time out and add 3s to boot time. […]
Hi Reka, I have tested using HDMI, C0 and C1 ports and the boot time is around 1s.
For cbmem timestamps please reference the bug in commit msg.
https://review.coreboot.org/c/coreboot/+/78146/comment/45edd209_41556076 :
PS1, Line 63: static const long display_timeout_ms = 3000;
:
: if (display_init_required()
: && !gpio_get(GPIO_USB_C0_HPD)) {
: /* This has to be done before FSP-S runs. */
: if (google_chromeec_wait_for_displayport(display_timeout_ms)){
: wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms);
: }
: }
: else if (display_init_required()
: && !gpio_get(GPIO_USB_C1_HPD)) {
: /* This has to be done before FSP-S runs. */
: if (google_chromeec_wait_for_displayport(display_timeout_ms)){
: wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms);
: }
: }
> It's better to implement this in a separate function, e.g. variant_display_init. […]
Done
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Hello Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78146?usp=email
to look at the new patch set (#2).
Change subject: mb/google/dedede/var/boxy: Add wait for HPD function
......................................................................
mb/google/dedede/var/boxy: Add wait for HPD function
Boxy project need to wait for HPD ready to continue boot in ramstage to
avoid no display in DEV screen and recovery screen
BUG=b:303346324
TEST=Both type-c ports can display in DEV screen and recovery screen
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9
---
M src/mainboard/google/dedede/variants/boxy/Makefile.inc
A src/mainboard/google/dedede/variants/boxy/mainboard.c
2 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/78146/2
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Change subject: mb/google/dedede/var/boxy: Add wait for HPD function
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/dedede/variants/boxy/ramstage.c:
https://review.coreboot.org/c/coreboot/+/78146/comment/0fbed1dd_e25bf3d2 :
PS1, Line 68: google_chromeec_wait_for_displayport
I just tested on dibbi and this always returns an error (-1) because EC_CMD_USB_PD_GET_AMODE is no longer implemented in TCPMv2 (https://crrev.com/c/4221975). I'm working on finding a solution.
https://review.coreboot.org/c/coreboot/+/78146/comment/07c9e212_b5606e04 :
PS1, Line 69: wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms);
If only C1 or HDMI is connected, I think this will always time out and add 3s to boot time. Have you tested these cases?
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Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78213?usp=email )
Change subject: mb/google/nissa/var/quandiso: Change camera fw_config feild
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78213/comment/e665e6da_478fdf61 :
PS3, Line 7: feild
> field
Will fix typo in the chromium cherry-pick commit.
https://review.coreboot.org/c/coreboot/+/78213/comment/4ea0580e_0dc0ce88 :
PS3, Line 9: reserve
> reserves
Will fix typo in the chromium cherry-pick commit.
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Change subject: mb/google/nissa/var/quandiso: Update SD card GPIO settings
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78253/comment/5cb75f1a_a8ab0788 :
PS3, Line 8:
> Why? Please elaborate.
Add more information in comment body and change the title.
File src/mainboard/google/brya/variants/quandiso/gpio.c:
https://review.coreboot.org/c/coreboot/+/78253/comment/e976a04d_00a75a41 :
PS3, Line 93: PAD_CFG_GPO(GPP_H12, 0, DEEP),
> This change not match the title. Also you should add the comment body.
Add more information in comment body and change the title.
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Change subject: mb/google/nissa/var/quandiso: Update SD card GPIO settings
......................................................................
mb/google/nissa/var/quandiso: Update SD card GPIO settings
Disable SD card GPIO with fw_config for quandiso units without SD
card and pull GPP_H12 to high to match the spec.
BUG=b:29656936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/quandiso/fw_config.c
M src/mainboard/google/brya/variants/quandiso/gpio.c
2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/78253/4
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Change subject: mb/google/dedede/var/boxy: Add wait for HPD function
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/dedede/variants/boxy/ramstage.c:
https://review.coreboot.org/c/coreboot/+/78146/comment/f27df7b6_e35a250e :
PS1, Line 63: static const long display_timeout_ms = 3000;
:
: if (display_init_required()
: && !gpio_get(GPIO_USB_C0_HPD)) {
: /* This has to be done before FSP-S runs. */
: if (google_chromeec_wait_for_displayport(display_timeout_ms)){
: wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms);
: }
: }
: else if (display_init_required()
: && !gpio_get(GPIO_USB_C1_HPD)) {
: /* This has to be done before FSP-S runs. */
: if (google_chromeec_wait_for_displayport(display_timeout_ms)){
: wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms);
: }
: }
It's better to implement this in a separate function, e.g. variant_display_init. Call this function from dedede/mainboard.c
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