coreboot-gerrit October 2023

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[S] Change in coreboot[master]: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
by Patrick Georgi (Code Review) 07 Oct '23

07 Oct '23

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78275?usp=email ) Change subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere ...................................................................... memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M src/mainboard/emulation/qemu-power9/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8186/include/soc/memlayout.ld M src/soc/mediatek/mt8188/include/soc/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/rockchip/rk3288/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld 18 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/78275/1 diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld index 8209433..d9c2a71 100644 --- a/src/mainboard/emulation/qemu-power9/memlayout.ld +++ b/src/mainboard/emulation/qemu-power9/memlayout.ld @@ -30,5 +30,5 @@ #if ENV_RAMSTAGE STACK(0xa000000, 32K) #endif - RAMSTAGE(0xa008000, 1M) + RAMSTAGE(0xa008000, 2M) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 7ec4892..b74c0bb 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -16,5 +16,5 @@ /* hole at (START + 8M + 14K, 50K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) - RAMSTAGE(START + 8M + 200K, 256K) + RAMSTAGE(START + 8M + 200K, 2M) } diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld index 41f0914..325524e 100644 --- a/src/soc/cavium/cn81xx/memlayout.ld +++ b/src/soc/cavium/cn81xx/memlayout.ld @@ -30,9 +30,9 @@ SRAM_END(BOOTROM_OFFSET + 0x80000) TTB(BOOTROM_OFFSET + 0x80000, 512K) - RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) + RAMSTAGE(BOOTROM_OFFSET + 0x100000, 2M) /* Stack for secondary CPUs */ - REGION(stack_sec, BOOTROM_OFFSET + 0x180000, + REGION(stack_sec, BOOTROM_OFFSET + 0x300000, CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) /* Leave some space for the payload */ diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index 8dce428..224dbda 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -42,5 +42,5 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) } diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index 3908426..c5d9d08 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -44,7 +44,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index f8bb0fa..f927b60 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -62,7 +62,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld index 8d1f2bd..ed3b71b 100644 --- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -66,7 +66,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 6c238c7..b1beef0 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -54,7 +54,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 322844d..06806c5 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -65,7 +65,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld index ed386f1..6f507ae 100644 --- a/src/soc/nvidia/tegra124/memlayout.ld +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -29,6 +29,6 @@ DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 128K) + RAMSTAGE(0x80200000, 2M) DMA_COHERENT(0x90000000, 2M) } diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index 55da129..e272c7d 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -32,6 +32,6 @@ DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 256K) + RAMSTAGE(0x80200000, 2M) TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) } diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld index e630e74..4b56060 100644 --- a/src/soc/qualcomm/ipq40xx/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -44,6 +44,6 @@ DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) POSTRAM_CBFS_CACHE(0x87280000, 512K) - RAMSTAGE(0x87300000, 512K) - DMA_COHERENT(0x87400000, 2M) + RAMSTAGE(0x87300000, 2M) + DMA_COHERENT(0x87500000, 2M) } diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld index 793e74e..43a51da 100644 --- a/src/soc/qualcomm/ipq806x/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/memlayout.ld @@ -32,7 +32,7 @@ SRAM_END(0x2A060000) DRAM_START(0x40000000) - RAMSTAGE(0x40640000, 128K) + RAMSTAGE(0x40640000, 2M) SYMBOL(memlayout_cbmem_top, 0x59F80000) POSTRAM_CBFS_CACHE(0x59F80000, 384K) DMA_COHERENT(0x5A000000, 2M) diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld index 348fb43..d883e24 100644 --- a/src/soc/qualcomm/qcs405/memlayout.ld +++ b/src/soc/qualcomm/qcs405/memlayout.ld @@ -35,5 +35,5 @@ /* DDR Carveout for BL31 usage */ REGION(dram_reserved, 0x85000000, 0x5100000, 4096) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 5e35a06..ea69a42 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -10,7 +10,7 @@ SECTIONS { DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) + RAMSTAGE(0x00200000, 2M) POSTRAM_CBFS_CACHE(0x01000000, 1M) DMA_COHERENT(0x10000000, 2M) FRAMEBUFFER(0x10800000, 8M) diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld index 142a892..c424692 100644 --- a/src/soc/samsung/exynos5250/memlayout.ld +++ b/src/soc/samsung/exynos5250/memlayout.ld @@ -27,7 +27,7 @@ SRAM_END(0x2078000) DRAM_START(0x40000000) - RAMSTAGE(0x40000000, 128K) + RAMSTAGE(0x40000000, 2M) POSTRAM_CBFS_CACHE(0x41000000, 8M) DMA_COHERENT(0x77300000, 1M) } diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld index 7c89413..240cdcd 100644 --- a/src/soc/samsung/exynos5420/memlayout.ld +++ b/src/soc/samsung/exynos5420/memlayout.ld @@ -28,7 +28,7 @@ SRAM_END(0x2074000) DRAM_START(0x20000000) - RAMSTAGE(0x20000000, 128K) + RAMSTAGE(0x20000000, 2M) POSTRAM_CBFS_CACHE(0x21000000, 8M) DMA_COHERENT(0x77300000, 1M) } diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index 73faa4b..8fc875d 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -22,7 +22,7 @@ DRAM_START(FU540_DRAM) REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 256K) - MEM_STACK(FU540_DRAM + 448K, 20K) - POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) + RAMSTAGE(FU540_DRAM + 128K, 2M) + MEM_STACK(FU540_DRAM + 128K + 2M, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/78275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Gerrit-Change-Number: 78275 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: amdfwtool: Set the table size as the sum of entries and header
by Bao Zheng (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78274?usp=email to review the following change. Change subject: amdfwtool: Set the table size as the sum of entries and header ...................................................................... amdfwtool: Set the table size as the sum of entries and header The Table size doesn't include the FWs themselves. Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/78274/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 6822b2a..92d0f80 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -651,7 +651,8 @@ break; case PSP_COOKIE: case PSPL2_COOKIE: - table_size = ctx->current - ctx->current_table; + table_size = ALIGN_UP(sizeof(dir->header) + count * sizeof(psp_directory_entry), + TABLE_ALIGNMENT); if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The PSP table size should be 4K aligned\n"); amdfwtool_cleanup(ctx); @@ -670,7 +671,8 @@ break; case BHD_COOKIE: case BHDL2_COOKIE: - table_size = ctx->current - ctx->current_table; + table_size = ALIGN_UP(sizeof(dir->header) + count * sizeof(bios_directory_entry), + TABLE_ALIGNMENT); if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The BIOS table size should be 4K aligned\n"); amdfwtool_cleanup(ctx); -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: cbfs: Restore 32-bit padding in cbfs_header
by Elyes Haouas (Code Review) 07 Oct '23

07 Oct '23

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78239?usp=email ) Change subject: cbfs: Restore 32-bit padding in cbfs_header ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: FYI: https://docs.kernel.org/process/deprecated.html#zero-length-and-one-element- -- To view, visit https://review.coreboot.org/c/coreboot/+/78239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4199dcc4823469c5986ac967a55b1c85cc62f780 Gerrit-Change-Number: 78239 Gerrit-PatchSet: 3 Gerrit-Owner: Ivan Jager Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 07 Oct 2023 10:23:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
by Patrick Georgi (Code Review) 07 Oct '23

07 Oct '23

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78273?usp=email ) Change subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere ...................................................................... memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M src/mainboard/emulation/spike-riscv/memlayout.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8186/include/soc/memlayout.ld M src/soc/mediatek/mt8188/include/soc/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/rockchip/rk3288/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld 17 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/78273/1 diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 7ec4892..b74c0bb 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -16,5 +16,5 @@ /* hole at (START + 8M + 14K, 50K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) - RAMSTAGE(START + 8M + 200K, 256K) + RAMSTAGE(START + 8M + 200K, 2M) } diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld index 41f0914..325524e 100644 --- a/src/soc/cavium/cn81xx/memlayout.ld +++ b/src/soc/cavium/cn81xx/memlayout.ld @@ -30,9 +30,9 @@ SRAM_END(BOOTROM_OFFSET + 0x80000) TTB(BOOTROM_OFFSET + 0x80000, 512K) - RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) + RAMSTAGE(BOOTROM_OFFSET + 0x100000, 2M) /* Stack for secondary CPUs */ - REGION(stack_sec, BOOTROM_OFFSET + 0x180000, + REGION(stack_sec, BOOTROM_OFFSET + 0x300000, CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) /* Leave some space for the payload */ diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index 8dce428..224dbda 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -42,5 +42,5 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) } diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index 3908426..c5d9d08 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -44,7 +44,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index f8bb0fa..f927b60 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -62,7 +62,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld index 8d1f2bd..ed3b71b 100644 --- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -66,7 +66,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 6c238c7..b1beef0 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -54,7 +54,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 322844d..06806c5 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -65,7 +65,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld index ed386f1..6f507ae 100644 --- a/src/soc/nvidia/tegra124/memlayout.ld +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -29,6 +29,6 @@ DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 128K) + RAMSTAGE(0x80200000, 2M) DMA_COHERENT(0x90000000, 2M) } diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index 55da129..e272c7d 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -32,6 +32,6 @@ DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 256K) + RAMSTAGE(0x80200000, 2M) TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) } diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld index e630e74..4b56060 100644 --- a/src/soc/qualcomm/ipq40xx/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -44,6 +44,6 @@ DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) POSTRAM_CBFS_CACHE(0x87280000, 512K) - RAMSTAGE(0x87300000, 512K) - DMA_COHERENT(0x87400000, 2M) + RAMSTAGE(0x87300000, 2M) + DMA_COHERENT(0x87500000, 2M) } diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld index 793e74e..43a51da 100644 --- a/src/soc/qualcomm/ipq806x/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/memlayout.ld @@ -32,7 +32,7 @@ SRAM_END(0x2A060000) DRAM_START(0x40000000) - RAMSTAGE(0x40640000, 128K) + RAMSTAGE(0x40640000, 2M) SYMBOL(memlayout_cbmem_top, 0x59F80000) POSTRAM_CBFS_CACHE(0x59F80000, 384K) DMA_COHERENT(0x5A000000, 2M) diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld index 348fb43..d883e24 100644 --- a/src/soc/qualcomm/qcs405/memlayout.ld +++ b/src/soc/qualcomm/qcs405/memlayout.ld @@ -35,5 +35,5 @@ /* DDR Carveout for BL31 usage */ REGION(dram_reserved, 0x85000000, 0x5100000, 4096) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 5e35a06..ea69a42 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -10,7 +10,7 @@ SECTIONS { DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) + RAMSTAGE(0x00200000, 2M) POSTRAM_CBFS_CACHE(0x01000000, 1M) DMA_COHERENT(0x10000000, 2M) FRAMEBUFFER(0x10800000, 8M) diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld index 142a892..c424692 100644 --- a/src/soc/samsung/exynos5250/memlayout.ld +++ b/src/soc/samsung/exynos5250/memlayout.ld @@ -27,7 +27,7 @@ SRAM_END(0x2078000) DRAM_START(0x40000000) - RAMSTAGE(0x40000000, 128K) + RAMSTAGE(0x40000000, 2M) POSTRAM_CBFS_CACHE(0x41000000, 8M) DMA_COHERENT(0x77300000, 1M) } diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld index 7c89413..240cdcd 100644 --- a/src/soc/samsung/exynos5420/memlayout.ld +++ b/src/soc/samsung/exynos5420/memlayout.ld @@ -28,7 +28,7 @@ SRAM_END(0x2074000) DRAM_START(0x20000000) - RAMSTAGE(0x20000000, 128K) + RAMSTAGE(0x20000000, 2M) POSTRAM_CBFS_CACHE(0x21000000, 8M) DMA_COHERENT(0x77300000, 1M) } diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index 73faa4b..8fc875d 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -22,7 +22,7 @@ DRAM_START(FU540_DRAM) REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 256K) - MEM_STACK(FU540_DRAM + 448K, 20K) - POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) + RAMSTAGE(FU540_DRAM + 128K, 2M) + MEM_STACK(FU540_DRAM + 128K + 2M, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/78273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Gerrit-Change-Number: 78273 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/brya/var/dochi: update gpio settings
by David Wu (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Lucas Chen, Morris Hsu, Nick Vaccaro, Paul Menzel, Subrata Banik. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78112?usp=email ) Change subject: mb/google/brya/var/dochi: update gpio settings ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78112/comment/0b00e83c_30a6c33c : PS5, Line 9: schematics > Do they have a revision? Revision number is 20230923 after check with EE. -- To view, visit https://review.coreboot.org/c/coreboot/+/78112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Gerrit-Change-Number: 78112 Gerrit-PatchSet: 5 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 07 Oct 2023 02:06:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/dedede: Create dexi variant
by David Wu (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Derek Huang, Kenneth Chan, Lucas Chen, Nick Vaccaro, Reka Norman, Ren Kuo, Ricky Chang, Sheng-Liang Pan, YH Lin, Zhuohao Lee. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78249?usp=email ) Change subject: mb/google/dedede: Create dexi variant ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I708a16cb864dca7309cb0201e7887af7456a4885 Gerrit-Change-Number: 78249 Gerrit-PatchSet: 5 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Sat, 07 Oct 2023 02:03:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Nick Vaccaro. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78009?usp=email ) Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... Patch Set 3: (2 comments) This change is ready for review. Patchset: PS3: Do you think that we can push this in so that we have a framework for building this board? I can add the details in later. File src/mainboard/google/brox/board_info.txt: https://review.coreboot.org/c/coreboot/+/78009/comment/a65888c4_9a4b44db : PS1, Line 2: Brya > Brox? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 07 Oct 2023 01:24:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
by Bill XIE (Code Review) 07 Oct '23

07 Oct '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78288?usp=email to look at the new patch set (#4). Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume ...................................................................... drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1"), Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via bisect). Further inspection shows that DRAM training result of GM45 is stored in CMOS above 128 bytes in raminit_receive_enable_calibration.c, for s3 resume to restore, but it will be erased by sanitize_cmos(), leaving only "untrained" result restored, so s3 resume will fail. However, resetting CMOS seems unnecessary during s3 resume. Now, cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again with these changes. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/drivers/pc80/rtc/option.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/78288/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Gerrit-Change-Number: 78288 Gerrit-PatchSet: 4 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
by Bill XIE (Code Review) 07 Oct '23

07 Oct '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78288?usp=email to look at the new patch set (#3). Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume ...................................................................... drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1"), Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via bisect), for DRAM training result of GM45 is stored in CMOS above 128 bytes in northbridge/intel/gm45/raminit_receive_enable_calibration.c, for s3 resume to restore, but it will be erased by sanitize_cmos(), leaving only "untrained" result restored, so s3 resume will fail. However, resetting CMOS seems unnecessary during s3 resume. Now, cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again with these changes. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/drivers/pc80/rtc/option.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/78288/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Gerrit-Change-Number: 78288 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: util/amdfwtool: Check for pkg-config presence
by Karthik Ramasubramanian (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Felix Held, Martin Roth, Raul Rangel. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78191?usp=email ) Change subject: util/amdfwtool: Check for pkg-config presence ...................................................................... Patch Set 3: (1 comment) File util/amdfwtool/Makefile: https://review.coreboot.org/c/coreboot/+/78191/comment/abf14c66_49055c71 : PS1, Line 26: shell > Hrmm, I think it was failing because CFLAGS was lazily evaluated. […] Done. Yes that was the reason. -- To view, visit https://review.coreboot.org/c/coreboot/+/78191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d604145c919e7f71680d1e095dc68cb21868319 Gerrit-Change-Number: 78191 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 07 Oct 2023 00:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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