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Change subject: drivers/smm_payload_interface: Add initial support for SMM payload
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
> We've talked about chain-loading payloads, and this seems like a perfect place to do that. […]
I'm assuming Ron didn't need to support S3 resume? The payload is not on the resume path, so here, coreboot performs SMBASE relocation to maintain SMM's integrity. Skipping this would result in SMM being unusable after S3 resume. It would even be possible for malicious ring-0-level code to take over SMM.
On this making coreboot "UEFI compliant": Yes, EDK2 is currently the only payload where we could intend to use this. But if one wants the payload to own SMM, there are a limited number of approaches to use. We must read CPU SMBASEs from the payload to use on S3 resume during relocation. Then, either the payload contains the small set of register definitions needed, which isn't great for maintainability and adding new SoC support, or we just use the fact that at compile-time, the preprocessor can include the right header for us, because selecting a board determines the SoC.
Either way, we've been looking into sharing SMM between coreboot and some payload SMI handlers, but progress is slow. EDK2's standalone MM is really buggy and I've been busy.
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Change subject: arch/arm64: Support calling a trusted monitor
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
File src/arch/arm64/monitor_services.c:
https://review.coreboot.org/c/coreboot/+/78284/comment/4804418d_bfc821e0 :
PS3, Line 18: if (current_el() == EL3) {
We need to push this function definition too.
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Change subject: soc/amd/phoenix/psp_verstage: Fix hash file names for VBOOT FW Slot B
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78236/comment/183c4021_65abaceb :
PS1, Line 7: Fix the hash file names
> Maybe: […]
Done
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Change subject: soc/amd/phoenix/psp_verstage: Fix hash file names for VBOOT FW Slot B
......................................................................
soc/amd/phoenix/psp_verstage: Fix hash file names for VBOOT FW Slot B
Fix the hash file names to be used to verify signed PSP binaries when
booting with VBOOT FW Slot B.
BUG=None
TEST=Build and boot to OS in Myst with PSP Verstage enabled using both
VBOOT slots A and B.
Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/phoenix/psp_verstage/chipset.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/78236/2
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Change subject: soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78231/comment/5f0e3173_79c485fd :
PS1, Line 7: Fix the PSP verstage timestamps
> Maybe more specific: […]
Done
https://review.coreboot.org/c/coreboot/+/78231/comment/123842b5_da1a3079 :
PS1, Line 9: CB:74016
> As git operates with hashes, I’d add that (and the summary). It’d be enough as a Fixes: tag.
Done
https://review.coreboot.org/c/coreboot/+/78231/comment/9aa78f2a_dbea6c17 :
PS1, Line 11: timestamps(in microseconds)
> Please add a space before (.
Done
https://review.coreboot.org/c/coreboot/+/78231/comment/9ec07aaf_9cbf582e :
PS1, Line 13: adjust
> adjusted
Done
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Change subject: soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
......................................................................
soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
Commit 26d54b70e282 ("soc/amd/common/cpu: use TSC_MONOTONIC_TIMER for
SOC_AMD_COMMON_BLOCK_TSC") updated all the AMD SoCs with Zen-based CPU
cores to use TSC_MONOTONIC_TIMER. The same change adjusted the PSP
Verstage timestamps (in microseconds) to the x86 TSC rate. But it
included only the base_time during the adjustment leaving the individual
entry timestamp. This leads to incorrectly adjusted PSP Verstage
timestamps. Fix the adjustment logic.
BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that the PSP Verstage
timestamps in cbmem -t output are adjusted correctly.
Before this change:
5:start of verified boot 67,890 (69,936)
503:starting to initialize TPM 67,890 (0)
504:finished TPM initialization 67,902 (12)
505:starting to verify keyblock/preamble (RSA) 67,906 (3)
506:finished verifying keyblock/preamble (RSA) 67,984 (77)
511:starting TPM PCR extend 67,984 (0)
512:finished TPM PCR extend 67,992 (7)
513:starting locking TPM 67,992 (0)
514:finished locking TPM 67,995 (3)
6:end of verified boot 67,995 (0)
11:start of bootblock 572,152 (504,156)
After this change:
5:start of verified boot 71,000 (73,040)
503:starting to initialize TPM 71,065 (65)
504:finished TPM initialization 101,506 (30,441)
505:starting to verify keyblock/preamble (RSA) 110,624 (9,118)
506:finished verifying keyblock/preamble (RSA) 297,101 (186,477)
511:starting TPM PCR extend 297,297 (196)
512:finished TPM PCR extend 315,338 (18,041)
513:starting locking TPM 315,341 (3)
514:finished locking TPM 322,922 (7,581)
6:end of verified boot 322,943 (21)
11:start of bootblock 570,296 (247,353)
Change-Id: I3e52bef22f65596152f29c511bed680427660ff5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/vboot/vboot_bootblock.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78231/3
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to look at the new patch set (#2).
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Change subject: soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
......................................................................
soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
Commit 26d54b7 (soc/amd/common/cpu: use TSC_MONOTONIC_TIMER for
SOC_AMD_COMMON_BLOCK_TSC) updated all the AMD SoCs with Zen-based CPU
cores to use TSC_MONOTONIC_TIMER. The same change adjusted the PSP
Verstage timestamps (in microseconds) to the x86 TSC rate. But it
included only the base_time during the adjustment leaving the individual
entry timestamp. This leads to incorrectly adjusted PSP Verstage
timestamps. Fix the adjustment logic.
BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that the PSP Verstage
timestamps in cbmem -t output are adjusted correctly.
Before this change:
5:start of verified boot 67,890 (69,936)
503:starting to initialize TPM 67,890 (0)
504:finished TPM initialization 67,902 (12)
505:starting to verify keyblock/preamble (RSA) 67,906 (3)
506:finished verifying keyblock/preamble (RSA) 67,984 (77)
511:starting TPM PCR extend 67,984 (0)
512:finished TPM PCR extend 67,992 (7)
513:starting locking TPM 67,992 (0)
514:finished locking TPM 67,995 (3)
6:end of verified boot 67,995 (0)
11:start of bootblock 572,152 (504,156)
After this change:
5:start of verified boot 71,000 (73,040)
503:starting to initialize TPM 71,065 (65)
504:finished TPM initialization 101,506 (30,441)
505:starting to verify keyblock/preamble (RSA) 110,624 (9,118)
506:finished verifying keyblock/preamble (RSA) 297,101 (186,477)
511:starting TPM PCR extend 297,297 (196)
512:finished TPM PCR extend 315,338 (18,041)
513:starting locking TPM 315,341 (3)
514:finished locking TPM 322,922 (7,581)
6:end of verified boot 322,943 (21)
11:start of bootblock 570,296 (247,353)
Change-Id: I3e52bef22f65596152f29c511bed680427660ff5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/vboot/vboot_bootblock.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78231/2
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Change subject: Add Intel maintainers for x86, soc/intel, FSP, ACPI
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Patch Set 3:
This change is ready for review.
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