coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: amdfwtool: Set the table size as the sum of entries and header
by Bao Zheng (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Martin Roth, Nikolai Vyssotski, Zheng Bao. Hello Martin Roth, Nikolai Vyssotski, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78274?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set the table size as the sum of entries and header ...................................................................... amdfwtool: Set the table size as the sum of entries and header The Table size doesn't include the FWs themselves. Set the table size earlier to make sure no other data be put into the table. Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 14 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/78274/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Disable package C-state auto demotion
by Subrata Banik (Code Review) 07 Oct '23

07 Oct '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78250?usp=email ) Change subject: mb/google/{rex,ovis}: Disable package C-state auto demotion ...................................................................... mb/google/{rex,ovis}: Disable package C-state auto demotion Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. BUG=b:303546334 TEST=Local build successfully & Boot to OS successfully - Also check platform enter PC8 state in local video playback - before this change: # iotools rdmsr 0 0xE2 -> 0x0000000060008008 - After # iotools rdmsr 0 0xE2 -> 0x0000000000008008 Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78250 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 4 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 6fc0dc0..7d39ece 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -36,6 +36,9 @@ # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" + # Disable PKGC-state demotion + register "disable_package_c_state_demotion" = "1" + # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index ec57ee7..5894fe6 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -36,6 +36,9 @@ # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" + # Disable PKGC-state demotion + register "disable_package_c_state_demotion" = "1" + # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index ec38e80..6210406 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -419,6 +419,8 @@ * Enable or Disable Package C-state Demotion. * Default is set to 0. * Set this to 1 in order to disable Package C-state demotion. + * NOTE: Un-Demotion from demoted Package C-state needs to be disabled + * when auto demotion is disabled. */ bool disable_package_c_state_demotion; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 5350783..5ec9cf4 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -666,6 +666,7 @@ s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion; s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; + s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion; s_cfg->PmcV1p05PhyExtFetControlEn = 1; /* Enable PCH to CPU energy report feature. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Gerrit-Change-Number: 78250 Gerrit-PatchSet: 5 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Disable package C-state auto demotion
by Subrata Banik (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Eran Mitrani, Sukumar Ghorai, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78250?usp=email ) Change subject: mb/google/{rex,ovis}: Disable package C-state auto demotion ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Verified. Looks good. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Gerrit-Change-Number: 78250 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 07 Oct 2023 14:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/{rex,ovis}: Disable package C-state auto demotion
by Subrata Banik (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Eran Mitrani, Sukumar Ghorai, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78250?usp=email ) Change subject: mb/google/{rex,ovis}: Disable package C-state auto demotion ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Gerrit-Change-Number: 78250 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 07 Oct 2023 14:58:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cbfs: Restore 32-bit padding in cbfs_header
by Patrick Georgi (Code Review) 07 Oct '23

07 Oct '23

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78239?usp=email ) Change subject: cbfs: Restore 32-bit padding in cbfs_header ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > FYI: https://docs.kernel.org/process/deprecated. […] That isn't the problem here, quite the opposite: The field is called "pad", so it serves as padding. That is: it exists for the sole purpose to ensure that the struct spans a certain size (also, pad fields can easily be repurposed in the future). The concern in that Linux doc (not that we care _too_ much about what Linux does) is that a trailing field is used as an accessor: ``` struct foo { ... char name[1] } ``` as a way to have a flexible length "name" field after foo that is easily accessed. That breaks down any sizeof() work that tries to determine the size of foo without the name. Again: not the thing this pad field is about. -- To view, visit https://review.coreboot.org/c/coreboot/+/78239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4199dcc4823469c5986ac967a55b1c85cc62f780 Gerrit-Change-Number: 78239 Gerrit-PatchSet: 3 Gerrit-Owner: Ivan Jager Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 07 Oct 2023 14:56:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal
by Stanley Wu (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Derek Huang, Joey Peng, Paul Menzel, Reka Norman. Stanley Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78146?usp=email ) Change subject: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal ...................................................................... Patch Set 9: (2 comments) File src/mainboard/google/dedede/variants/boxy/ramstage.c: https://review.coreboot.org/c/coreboot/+/78146/comment/2ad3bbe4_1ebd869b : PS8, Line 68: > new patch 9 for configuring GPIO_HDMI_HPD to input and get correct state. Done https://review.coreboot.org/c/coreboot/+/78146/comment/ce9a61e1_45442885 : PS8, Line 69: if (display_init_required() : && !gpio_get(GPIO_USB_C0_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms); : } else if (display_init_required() : && !gpio_get(GPIO_USB_C1_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms); : } > Upload patch 9 to remove wait_for_hpd() and add 3s delay directly with non-HDMI display case due to […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9 Gerrit-Change-Number: 78146 Gerrit-PatchSet: 9 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 07 Oct 2023 14:26:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal
by Stanley Wu (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Derek Huang, Joey Peng, Paul Menzel, Reka Norman. Stanley Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78146?usp=email ) Change subject: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal ...................................................................... Patch Set 8: (4 comments) File src/mainboard/google/dedede/variants/boxy/ramstage.c: https://review.coreboot.org/c/coreboot/+/78146/comment/3fbb0e16_4e4498b8 : PS8, Line 68: > Are you sure we can get the correct gpio state by get_gpio() without configuring the gpio to input? new patch 9 for configuring GPIO_HDMI_HPD to input and get correct state. https://review.coreboot.org/c/coreboot/+/78146/comment/a23b7dcb_df3d0eec : PS8, Line 70: && !gpio_get(GPIO_USB_C0_HPD) > this is redundant. Done https://review.coreboot.org/c/coreboot/+/78146/comment/1a3b1d97_e45939d9 : PS8, Line 74: && !gpio_get(GPIO_USB_C1_HPD > this is redundant Done https://review.coreboot.org/c/coreboot/+/78146/comment/b324350c_e033ed5a : PS8, Line 69: if (display_init_required() : && !gpio_get(GPIO_USB_C0_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms); : } else if (display_init_required() : && !gpio_get(GPIO_USB_C1_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms); : } > If only HDMI is connected, these will always timeout and add 6s delay. […] Upload patch 9 to remove wait_for_hpd() and add 3s delay directly with non-HDMI display case due to Boxy display output only have HDMI or typC port C1/C2 case, and C1/C2 case should waiting 3s for USBC dongle -- To view, visit https://review.coreboot.org/c/coreboot/+/78146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9 Gerrit-Change-Number: 78146 Gerrit-PatchSet: 8 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 07 Oct 2023 14:26:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal
by Joey Peng (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Joey Peng, Paul Menzel, Reka Norman. Hello Derek Huang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78146?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal ...................................................................... mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal Boxy project needs to wait for HPD ready to continue boot in ramstage to avoid no display in DEV screen and recovery screen. BUG=b:303346324 TEST=Both type-c ports can display in DEV screen and recovery screen Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9 --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/boxy/ramstage.c 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/78146/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/78146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9 Gerrit-Change-Number: 78146 Gerrit-PatchSet: 9 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
by Patrick Georgi (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Hung-Te Lin, Julius Werner, Philipp Hug, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich. Hello Hung-Te Lin, Julius Werner, Philipp Hug, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78273?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere ...................................................................... memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M src/mainboard/emulation/qemu-power9/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8186/include/soc/memlayout.ld M src/soc/mediatek/mt8188/include/soc/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/rockchip/rk3288/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld 18 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/78273/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Gerrit-Change-Number: 78273 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Kconfig: Bring HEAP_SIZE to a common, large value
by Patrick Georgi (Code Review) 07 Oct '23

07 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Werner Zeh, ron minnich. Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78276?usp=email ) Change subject: Kconfig: Bring HEAP_SIZE to a common, large value ...................................................................... Kconfig: Bring HEAP_SIZE to a common, large value We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M src/Kconfig M src/cpu/qemu-x86/Kconfig M src/mainboard/sifive/hifive-unleashed/Kconfig M src/northbridge/amd/pi/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig 20 files changed, 1 insertion(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/78276/1 diff --git a/src/Kconfig b/src/Kconfig index 1549719..ae80240 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -751,8 +751,7 @@ config HEAP_SIZE hex - default 0x100000 if FLATTENED_DEVICE_TREE - default 0x4000 + default 0x100000 config STACK_SIZE hex diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index f3e2c4c..0fa999e 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -35,7 +35,4 @@ default 32 if SMM_TSEG default 4 -config HEAP_SIZE - default 0x8000 - endif diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 7f9300f..7bc3b0b 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -10,9 +10,6 @@ select FLATTENED_DEVICE_TREE select SPI_SDCARD -config HEAP_SIZE - default 0x10000 - config MAINBOARD_DIR default "sifive/hifive-unleashed" diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 4518db1..4ffe82a 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -29,8 +29,4 @@ hex default 0x200000 -config HEAP_SIZE - hex - default 0xc0000 - endif # NORTHBRIDGE_AMD_PI diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 796fe4e..c33f287 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -264,10 +264,6 @@ bool default n -config HEAP_SIZE - hex - default 0xc0000 - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 9af7455..6ff135e 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -152,10 +152,6 @@ bool default n -config HEAP_SIZE - hex - default 0xc0000 - config EHCI_BAR hex default 0xfef00000 diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 368581f..77ca972 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -30,9 +30,6 @@ int default 1 -config HEAP_SIZE - default 0x10000 - config STACK_SIZE default 0x2000 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 82ec8f2..4b960c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -215,11 +215,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x80000 if BMP_LOGO - default 0x10000 - config GFX_GMA_DEFAULT_MMIO default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bce935d..78ec298 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -252,10 +252,6 @@ help Name of file to store in the IFWI region. -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 6 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 80237f9..a42a3c3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -160,10 +160,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x8000 - config NHLT_DMIC_1CH_16B bool depends on ACPI_NHLT diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7f1c767..3361c0d 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -104,10 +104,6 @@ hex default 0x0 -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 7 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index ff5def3..3d84991 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -106,10 +106,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 8 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 48030a1..590e8b8 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -197,11 +197,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x80000 if BMP_LOGO - default 0x10000 - # Intel recommends reserving the PCIe TBT root port resources as below: # - 42 buses # - 194 MiB Non-prefetchable memory diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d6a11363e..e0df501 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -151,10 +151,6 @@ help If you set this option to n, will not use native SD controller. -config HEAP_SIZE - hex - default 0x80000 - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0a4b7bf..c07a0d8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -152,10 +152,6 @@ config INTEL_TME default n -config HEAP_SIZE - hex - default 0x10000 - config MAX_ROOT_PORTS int default 24 if SOC_INTEL_TIGERLAKE_PCH_H diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 63ced01..e63bee5 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -91,10 +91,6 @@ config ECAM_MMCONF_BUS_NUMBER default 256 -config HEAP_SIZE - hex - default 0x80000 - config HPET_MIN_TICKS hex default 0x80 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index f54f771..ac166c3 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -71,10 +71,6 @@ hex default 0x7C00 -config HEAP_SIZE - hex - default 0x80000 - config STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index c2c3d4e..5d84387 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -55,10 +55,6 @@ hex default 0x7C00 -config HEAP_SIZE - hex - default 0x80000 - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b1c4c78..43b87ad 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -79,10 +79,6 @@ hex default 0x8c00 -config HEAP_SIZE - hex - default 0x80000 - config STACK_SIZE hex default 0x4000 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 0eabb00..0ce9273 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -57,8 +57,4 @@ help Path for utils to combine SBL_ELF and bootblock -config HEAP_SIZE - hex - default 0x8000 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/78276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Gerrit-Change-Number: 78276 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit October 2023