coreboot-gerrit October 2023

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Follow PCH BIOS spec
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Felix Held, Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78225?usp=email ) Change subject: sb/intel/bd82x6x: Follow PCH BIOS spec ...................................................................... Patch Set 4: (1 comment) File src/southbridge/intel/bd82x6x/early_pch.c: https://review.coreboot.org/c/coreboot/+/78225/comment/05dcd1e7_f52714b6 : PS3, Line 139: 0x1e58 > might be good to add a define for this to avoid having a magic constant in here to make it a bit mor […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Gerrit-Change-Number: 78225 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 08 Oct 2023 11:09:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x/pcie: Use defines
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78293?usp=email ) Change subject: sb/intel/bd82x6x/pcie: Use defines ...................................................................... sb/intel/bd82x6x/pcie: Use defines Use defines instead of magic values. Test: Lenovo X220 still boots and all PCIe devices are still working. Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/78293/1 diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 599d5d9..965bc81 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -125,9 +125,11 @@ reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ pci_write_config32(dev, 0xd8, reg32); + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + /* Adjust ASPM L1 exit latency */ - reg32 = pci_read_config32(dev, 0x4c); - reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); + reg32 = pci_read_config32(dev, cap + PCI_EXP_LNKCAP); + reg32 &= ~PCI_EXP_LNKCAP_L1EL; if (RCBA32(CIR9) & (1 << 16)) { /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ reg32 |= (1 << 17); @@ -135,11 +137,9 @@ /* Else set ASPM L1 to 2-4us */ reg32 |= (1 << 16); } - pci_write_config32(dev, 0x4c, reg32); + pci_write_config32(dev, cap + PCI_EXP_LNKCAP, reg32); /* Set slot power limit as configured above */ - cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP); if (pci_is_hotplugable(dev)) reg32 |= (PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC); -- To view, visit https://review.coreboot.org/c/coreboot/+/78293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18 Gerrit-Change-Number: 78293 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: lib/smbios: Improve Type9
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78292?usp=email ) Change subject: lib/smbios: Improve Type9 ...................................................................... lib/smbios: Improve Type9 Scan for PCI capabilities and update the characteristics 2 field in SMBIOS type 9 accordingly. Test: Lenovo X220 still boots fine, dmidecode -t 9 shows no difference though. Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/smbios.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/78292/1 diff --git a/src/lib/smbios.c b/src/lib/smbios.c index deee193b..9a1547c 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -1127,6 +1127,9 @@ enum slot_data_bus_bandwidth bandwidth; enum misc_slot_type type; enum misc_slot_length length; + uint8_t characteristics_2 = 0; + unsigned int cap; + uint16_t sltcap, pmecap; if (dev->path.type != DEVICE_PATH_PCI) return 0; @@ -1157,6 +1160,20 @@ else length = SlotLengthUnknown; + cap = pci_find_capability(dev, PCI_CAP_ID_PM); + if (cap > 0) { + pmecap = pci_read_config16(dev, cap + PCI_PM_PMC); + if (pmecap & PCI_PM_CAP_PME) + characteristics_2 |= SMBIOS_SLOT_PME; + } + + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (cap > 0) { + sltcap = pci_read_config16(dev, cap + PCI_EXP_SLTCAP); + if (sltcap & PCI_EXP_SLTCAP_HPC) + characteristics_2 |= SMBIOS_SLOT_HOTPLUG; + } + return smbios_write_type9(current, handle, dev->smbios_slot_designation, type, @@ -1165,7 +1182,7 @@ length, 0, 1, - 0, + characteristics_2, dev->bus->secondary, dev->path.pci.devfn); } -- To view, visit https://review.coreboot.org/c/coreboot/+/78292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e Gerrit-Change-Number: 78292 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/lenovo/x220: Update devicetree
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Alexander Couzens. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78291?usp=email ) Change subject: mb/lenovo/x220: Update devicetree ...................................................................... mb/lenovo/x220: Update devicetree - Disable unconnected PCH PCIe ports 1 + 3. - Add smbios_slot_desc to WLAN PCIe port - Add comment for PCIe port 7 that might have a XHCI controller connected (some variants only). Test: Lenovo X220 still boots and all devices are still working fine. The WLAN slot is shown in dmidecode -t 9. Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/x220/devicetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/78291/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 7a99599..4c8c12f 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -57,9 +57,12 @@ end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 device ref hda on end # High Definition Audio - device ref pcie_rp1 on end # PCIe Port #1 - device ref pcie_rp2 on end # PCIe Port #2 (wlan) - device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on # PCIe Port #2 (wlan) + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort" + "WIFI" "SlotDataBusWidth1X" + end + device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 @@ -71,7 +74,7 @@ end end # PCIe Port #5 (SD) device ref pcie_rp6 off end # PCIe Port #6 - device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp7 on end # PCIe Port #7 Optional XHCI controller device ref pcie_rp8 off end # PCIe Port #8 device ref ehci1 on end # USB2 EHCI #1 device ref pci_bridge off end # PCI bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/78291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff Gerrit-Change-Number: 78291 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Disable unused PCIe root ports
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Hello Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78226?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Kyösti Mälkki, Verified+1 by build bot (Jenkins) Change subject: sb/intel/bd82x6x: Disable unused PCIe root ports ...................................................................... sb/intel/bd82x6x: Disable unused PCIe root ports Follow the PCH BIOS spec more closely by porting the broadwell and braswell PCIe downstream device detection. To safe power disable PCIe root ports that have no downstream device connected. By setting the FLAGS_SLOT bit in register PCI_EXP_FLAGS the PCI_EXP_SLTSTA_PDS bit will be updated with in band device detection from the PCIe PHY. While this is primarly used for PCIe hot-plug detection, it is more reliable than probing for downstream devices by reading DID/VID PCI registers. The FLAGS_SLOT bit should stay cleared for integrated devices, as those are known to be present, but to simplify the code all PCIe ports will have the FLAGS_SLOT bit set. There currently used devicetrees might also be lacking integrated devices on the PCH root ports... The SLOTCAP field must be updated by BIOS when the FLAGS_SLOT is set, but it shouldn't be filled for integrated devices. Until now the SLOTCAP field has always been populated and it never was a problem. - Set FLAGS_SLOT "Slot Implemented" bit early. - Read bit PCI_EXP_SLTSTA_PDS to detect connected downstream devices as done on braswell. - Disable unused PCIe slots that are not hotplugable. - Set BIT26 in register 0x338 and wait for bits in register 0x328 to clear as done on broadwell. Test: Tested on Lenovo X220. Unused root ports are disabled and port that are in used or marked hot-plug are kept enabled. Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/pch.c 1 file changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/78226/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Gerrit-Change-Number: 78226 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Follow PCH BIOS spec
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Felix Held, Kyösti Mälkki, Patrick Rudolph. Hello Felix Held, Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78225?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Code-Review+2 by Kyösti Mälkki, Verified+1 by build bot (Jenkins) Change subject: sb/intel/bd82x6x: Follow PCH BIOS spec ...................................................................... sb/intel/bd82x6x: Follow PCH BIOS spec PCH BIOS spec says that BIOS must clear BIT26 in register 0x338 in PEI, as done on lynxpoint. Copy and adapt the lynxpoint code to do the same on bd82x6x. Add special case for UM77 chipset, which only has 4 PCIe ports. Test: System still boots and all PCIe ports are fully working. Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/78225/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Gerrit-Change-Number: 78225 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: configurable slp-s0 residency counter frequency in LPIT table
by Paul Menzel (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: configurable slp-s0 residency counter frequency in LPIT table ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78164/comment/3bdb116b_358ab6ed : PS14, Line 7: configurable slp-s0 residency counter frequency in LPIT table Please make it a statement by adding a verb (in imperative mood). Maybe: Make … configurable or Allow to configure … -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 14 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 09:10:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/rex/var/screebo: Update DTT settings for thermal control
by zhongtian wu (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Kun Liu, Subrata Banik, Tarun. zhongtian wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78290?usp=email ) Change subject: mb/google/rex/var/screebo: Update DTT settings for thermal control ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Gerrit-Change-Number: 78290 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 07:54:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/rex/var/screebo: Update DTT settings for thermal control
by Kun Liu (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Kun Liu, Subrata Banik, Tarun. Hello Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78290?usp=email to look at the new patch set (#2). Change subject: mb/google/rex/var/screebo: Update DTT settings for thermal control ...................................................................... mb/google/rex/var/screebo: Update DTT settings for thermal control update DTT settings for thermal control BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/78290/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Gerrit-Change-Number: 78290 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2023