coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal
by Reka Norman (Code Review) 09 Oct '23

09 Oct '23

Attention is currently required from: Derek Huang, Joey Peng, Paul Menzel, Stanley Wu. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78146?usp=email ) Change subject: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/dedede/variants/boxy/ramstage.c: https://review.coreboot.org/c/coreboot/+/78146/comment/784922d5_d8c776a1 : PS8, Line 69: if (display_init_required() : && !gpio_get(GPIO_USB_C0_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms); : } else if (display_init_required() : && !gpio_get(GPIO_USB_C1_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms); : } > Done The code above would still add an unconditional 3s delay when only C1 is connected right? I think it's better to wait for all HPD signals at the same time. I've uploaded a CL for all dibbi variants here: https://review.coreboot.org/c/coreboot/+/78294. Please test it on boxy. -- To view, visit https://review.coreboot.org/c/coreboot/+/78146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9 Gerrit-Change-Number: 78146 Gerrit-PatchSet: 9 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Oct 2023 00:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/dedede: Wait for HPD on dibbi variants
by Reka Norman (Code Review) 09 Oct '23

09 Oct '23

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78294?usp=email ) Change subject: mb/google/dedede: Wait for HPD on dibbi variants ...................................................................... mb/google/dedede: Wait for HPD on dibbi variants Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. TEST=On dibbi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Id4657b5d5a95a68ecbd9efcf3585cf96ad1e13e1 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/boxy/gpio.c M src/mainboard/google/dedede/variants/dibbi/gpio.c M src/mainboard/google/dedede/variants/taranza/gpio.c 6 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78294/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index a0a537c..40c6088 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -3,12 +3,15 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <drivers/tpm/cr50.h> #include <ec/ec.h> #include <security/tpm/tss.h> #include <soc/soc_chip.h> +#include <timer.h> #include <vb2_api.h> static void mainboard_update_soc_chip_config(void) @@ -30,12 +33,60 @@ } } +static bool any_hpd_ready(const gpio_t *gpios, size_t num_gpios) +{ + for (size_t i = 0; i < num_gpios; i++) { + if (gpio_get(gpios[i])) + return true; + } + + return false; +} + +static void mainboard_wait_for_hpd(void) +{ + static const long display_timeout_ms = 3000; + struct stopwatch sw; + size_t num_gpios; + const gpio_t *hpd_gpios = variant_hpd_gpios(&num_gpios); + + if (num_gpios == 0) + printk(BIOS_WARNING, "No HPD GPIOs, skip waiting\n"); + + printk(BIOS_INFO, "Waiting for HPD\n"); + + /* Pins will be configured back by gpio_configure_pads. */ + for (size_t i = 0; i < num_gpios; i++) { + gpio_input(hpd_gpios[i]); + } + + stopwatch_init_msecs_expire(&sw, display_timeout_ms); + while (!any_hpd_ready(hpd_gpios, num_gpios)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ld ms. Abort.\n", + display_timeout_ms); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lld ms\n", + stopwatch_duration_msecs(&sw)); +} + static void mainboard_init(void *chip_info) { const struct pad_config *base_pads; const struct pad_config *override_pads; size_t base_num, override_num; + /* + * For chromeboxes, wait for DP HPD to be asserted before + * entering FSP-S, otherwise display init may fail. + */ + if (!CONFIG(SYSTEM_TYPE_LAPTOP) && display_init_required()) + mainboard_wait_for_hpd(); + base_pads = baseboard_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index f377d9a..557f6bf 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -489,3 +489,9 @@ }; DECLARE_WEAK_CROS_GPIOS(cros_gpios); + +const gpio_t *__weak variant_hpd_gpios(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index b258481..bb9fd5d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -15,6 +15,7 @@ const struct pad_config *variant_sleep_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); const struct pad_config *variant_romstage_gpio_table(size_t *num); +const gpio_t *variant_hpd_gpios(size_t *num); enum s0ix_entry { S0IX_EXIT, diff --git a/src/mainboard/google/dedede/variants/boxy/gpio.c b/src/mainboard/google/dedede/variants/boxy/gpio.c index f8ed0cf..e8cb9ff 100644 --- a/src/mainboard/google/dedede/variants/boxy/gpio.c +++ b/src/mainboard/google/dedede/variants/boxy/gpio.c @@ -87,3 +87,18 @@ *num = ARRAY_SIZE(gpio_table); return gpio_table; } + +static const gpio_t hpd_gpios[] = { + /* HDMI1 */ + GPP_A17, + /* USB C0 */ + GPP_B23, + /* USB C1 */ + GPP_A16, +}; + +const gpio_t *variant_hpd_gpios(size_t *num) +{ + *num = ARRAY_SIZE(hpd_gpios); + return hpd_gpios; +} diff --git a/src/mainboard/google/dedede/variants/dibbi/gpio.c b/src/mainboard/google/dedede/variants/dibbi/gpio.c index 89a7a77..2998592 100644 --- a/src/mainboard/google/dedede/variants/dibbi/gpio.c +++ b/src/mainboard/google/dedede/variants/dibbi/gpio.c @@ -91,3 +91,18 @@ *num = ARRAY_SIZE(gpio_table); return gpio_table; } + +static const gpio_t hpd_gpios[] = { + /* HDMI1 */ + GPP_A17, + /* HDMI2 */ + GPP_A16, + /* USB C0 */ + GPP_B23, +}; + +const gpio_t *variant_hpd_gpios(size_t *num) +{ + *num = ARRAY_SIZE(hpd_gpios); + return hpd_gpios; +} diff --git a/src/mainboard/google/dedede/variants/taranza/gpio.c b/src/mainboard/google/dedede/variants/taranza/gpio.c index 89a7a77..2998592 100644 --- a/src/mainboard/google/dedede/variants/taranza/gpio.c +++ b/src/mainboard/google/dedede/variants/taranza/gpio.c @@ -91,3 +91,18 @@ *num = ARRAY_SIZE(gpio_table); return gpio_table; } + +static const gpio_t hpd_gpios[] = { + /* HDMI1 */ + GPP_A17, + /* HDMI2 */ + GPP_A16, + /* USB C0 */ + GPP_B23, +}; + +const gpio_t *variant_hpd_gpios(size_t *num) +{ + *num = ARRAY_SIZE(hpd_gpios); + return hpd_gpios; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4657b5d5a95a68ecbd9efcf3585cf96ad1e13e1 Gerrit-Change-Number: 78294 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/common: Refactor BERT generation flow for crashlog
by Subrata Banik (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Kane Chen, Kapil Porwal, Pratikkumar V Prajapati. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78257?usp=email ) Change subject: soc/intel/common: Refactor BERT generation flow for crashlog ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/acpi_bert.c: https://review.coreboot.org/c/coreboot/+/78257/comment/4d2bc4e5_ea16803f : PS2, Line 29: cl_acpi_data > Not needed, because new_cper_fw_error_crashlog will allocate the BERT storage at line# 75. This is just a temp pointer. noted! -- To view, visit https://review.coreboot.org/c/coreboot/+/78257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Gerrit-Change-Number: 78257 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 16:06:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
by Subrata Banik (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Paul Menzel, Ravishankar Sarawadi, Tarun, Utkarsh H Patel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email ) Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Gerrit-Change-Number: 78163 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 16:03:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/rex/var/screebo: Update DTT settings for thermal control
by Subrata Banik (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Kun Liu, Tarun, yunhao wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78290?usp=email ) Change subject: mb/google/rex/var/screebo: Update DTT settings for thermal control ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Gerrit-Change-Number: 78290 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 16:02:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: Disable package C-state auto demotion
by Subrata Banik (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Sukumar Ghorai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78278?usp=email ) Change subject: mb/intel/mtlrvp: Disable package C-state auto demotion ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: can u rebase this on ToT and break the chain ? -- To view, visit https://review.coreboot.org/c/coreboot/+/78278?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ff408280178a24686180f72f79522d2741607a1 Gerrit-Change-Number: 78278 Gerrit-PatchSet: 2 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 16:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/mtl: Set slp-s0 counter frequency
by Subrata Banik (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Sukumar Ghorai, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78277?usp=email ) Change subject: soc/intel/mtl: Set slp-s0 counter frequency ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/78277/comment/75de2067_a0840219 : PS1, Line 458: 8197 nit: ~8.2KHz? -- To view, visit https://review.coreboot.org/c/coreboot/+/78277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e95cd69e941d4d72d5c36a07660ca07ee2499ba Gerrit-Change-Number: 78277 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 16:01:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: configurable slp-s0 residency counter frequency in LPIT table
by Subrata Banik (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: configurable slp-s0 residency counter frequency in LPIT table ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 14 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 16:00:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email ) Change subject: sb/intel/bd82x6x: Improve SLCAP ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/bd82x6x/pcie.c: https://review.coreboot.org/c/coreboot/+/78228/comment/7f89e25a_5172637d : PS2, Line 152: reg32 |= (slot_number++ << 19); > Yes, I left a request on another commit to leave a comment that we don't follow the specs when we un […] It starts now counting at 1. I've added a hack that works when GENERATE_SMBIOS_TABLES is true to detect if it's a slot. -- To view, visit https://review.coreboot.org/c/coreboot/+/78228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Gerrit-Change-Number: 78228 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 11:10:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Disable unused PCIe root ports
by Patrick Rudolph (Code Review) 08 Oct '23

08 Oct '23

Attention is currently required from: Kyösti Mälkki. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78226?usp=email ) Change subject: sb/intel/bd82x6x: Disable unused PCIe root ports ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/bd82x6x/pch.c: https://review.coreboot.org/c/coreboot/+/78226/comment/56f23edc_6c20aec2 : PS2, Line 309: pci_or_config16(dev, cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_SLOT); > (I failed to copy-paste this correctly with previous review score) […] Added more details to commit message and code. -- To view, visit https://review.coreboot.org/c/coreboot/+/78226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Gerrit-Change-Number: 78226 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 08 Oct 2023 11:09:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2023