coreboot-gerrit October 2023

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[M] Change in coreboot[main]: soc/amd/*/Kconfig: rework SPL options
by Matt DeVillier (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78309?usp=email ) Change subject: soc/amd/*/Kconfig: rework SPL options ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/78309/comment/e9e61008_2c4004b7 : PS4, Line 36: actutal actual -- To view, visit https://review.coreboot.org/c/coreboot/+/78309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12fd8775db66f16fe632674cd67c6af483e8d4e2 Gerrit-Change-Number: 78309 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Oct 2023 18:07:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: add root complex support code
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78307?usp=email ) Change subject: soc/amd/genoa: add root complex support code ...................................................................... soc/amd/genoa: add root complex support code This functionality will eventually be used by the common data fabric domain resource reporting code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ieedd432c144e53e43d8099ec617a15056bb36fd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78307 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/root_complex.c 2 files changed, 63 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index ef8f349..2877fea 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -14,6 +14,7 @@ ramstage-y += aoac.c ramstage-y += chip.c +ramstage-y += root_complex.c CPPFLAGS_common += -I$(src)/soc/amd/genoa/include diff --git a/src/soc/amd/genoa/root_complex.c b/src/soc/amd/genoa/root_complex.c new file mode 100644 index 0000000..7dd1f82 --- /dev/null +++ b/src/soc/amd/genoa/root_complex.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/data_fabric.h> +#include <amdblocks/root_complex.h> +#include <console/console.h> +#include <device/device.h> +#include <types.h> + +uint32_t get_iohc_misc_smn_base(struct device *domain) +{ + switch (domain->path.domain.domain) { + case 0: + return SMN_IOHC_MISC_BASE_13C1; + case 1: + return SMN_IOHC_MISC_BASE_13B1; + case 2: + return SMN_IOHC_MISC_BASE_13E1; + case 3: + return SMN_IOHC_MISC_BASE_13D1; + default: + printk(BIOS_ERR, "Invalid domain 0x%x with no corresponding IOHC device.\n", + domain->path.domain.domain); + return 0; + } +} + +static const struct non_pci_mmio_reg non_pci_mmio[] = { + { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we + tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB + resource. */ + { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, + { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, + { 0x310, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, +}; + +const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) +{ + *count = ARRAY_SIZE(non_pci_mmio); + return non_pci_mmio; +} + +signed int get_iohc_fabric_id(struct device *domain) +{ + switch (domain->path.domain.domain) { + case 0: + return 0x22; + case 1: + return 0x23; + case 2: + return 0x21; + case 3: + return 0x20; + default: + return -1; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78307?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieedd432c144e53e43d8099ec617a15056bb36fd1 Gerrit-Change-Number: 78307 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa/include: add data_fabric.h
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78306?usp=email ) Change subject: soc/amd/genoa/include: add data_fabric.h ...................................................................... soc/amd/genoa/include: add data_fabric.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78306 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- A src/soc/amd/genoa/include/soc/data_fabric.h 1 file changed, 124 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/amd/genoa/include/soc/data_fabric.h b/src/soc/amd/genoa/include/soc/data_fabric.h new file mode 100644 index 0000000..6388926 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/data_fabric.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_DATA_FABRIC_H +#define AMD_GENOA_DATA_FABRIC_H + +#include <amdblocks/data_fabric_defs.h> +#include <types.h> + +#define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) +#define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) + +#define DF_PCI_CFG_MAP_COUNT 8 + +#define DF_PCI_CFG_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg)) +#define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg)) + +union df_pci_cfg_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 6; /* [ 2.. 7] */ + uint32_t segment_num : 8; /* [ 8..15] */ + uint32_t bus_num_base : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +union df_pci_cfg_limit { + struct { + uint32_t dst_fabric_id : 12; /* [ 0..11] */ + uint32_t : 4; /* [12..15] */ + uint32_t bus_num_limit : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_BASE0 DF_REG_ID(0, 0xd00) +#define DF_IO_LIMIT0 DF_REG_ID(0, 0xd04) + +#define DF_IO_REG_COUNT 8 + +#define DF_IO_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg)) +#define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg)) + +union df_io_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 3; /* [ 2.. 4] */ + uint32_t ie : 1; /* [ 5.. 5] */ + uint32_t : 10; /* [ 6..15] */ + uint32_t io_base : 13; /* [16..28] */ + uint32_t : 3; /* [29..31] */ + }; + uint32_t raw; +}; + +union df_io_limit { + struct { + uint32_t dst_fabric_id : 12; /* [ 0..11] */ + uint32_t : 4; /* [12..15] */ + uint32_t io_limit : 13; /* [16..28] */ + uint32_t : 3; /* [29..31] */ + }; + uint32_t raw; +}; + +#define DF_IO_ADDR_SHIFT 12 + +#define DF_MMIO_BASE0 DF_REG_ID(0, 0xd80) +#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xd84) +#define DF_MMIO_SHIFT 16 +#define DF_MMIO_CTRL0 DF_REG_ID(0, 0xd88) +#define DF_MMIO_ADDR_EXT0 DF_REG_ID(0, 0xd8c) +#define DF_MMIO_EXT_ADDR_SHIFT 48 + +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 16 + +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 1; /* [ 2.. 2] */ + uint32_t np : 1; /* [ 3.. 3] */ + uint32_t : 12; /* [ 4..15] */ + uint32_t dst_fabric_id : 12; /* [16..27] */ + uint32_t : 4; /* [28..31] */ + }; + uint32_t raw; +}; + +union df_mmio_addr_ext { + struct { + uint32_t base_ext : 8; /* [ 0.. 7] */ + uint32_t : 8; /* [ 8..15] */ + uint32_t limit_ext : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t reg_num : 10; /* [10.. 1] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + +#endif /* AMD_GENOA_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a Gerrit-Change-Number: 78306 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/amd/onyx: Use BMC SOL by default
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76509?usp=email ) Change subject: mb/amd/onyx: Use BMC SOL by default ...................................................................... mb/amd/onyx: Use BMC SOL by default Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Iefe61d25367bbe5cff0cacbfbafa32607de77d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76509 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/onyx/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/onyx/Kconfig b/src/mainboard/amd/onyx/Kconfig index ebefa5c..e724d14 100644 --- a/src/mainboard/amd/onyx/Kconfig +++ b/src/mainboard/amd/onyx/Kconfig @@ -16,4 +16,8 @@ config MAINBOARD_PART_NUMBER default "Onyx" +# Use BMC SOL console on SoC UART1 by default +config UART_FOR_CONSOLE + default 1 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/76509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefe61d25367bbe5cff0cacbfbafa32607de77d0f Gerrit-Change-Number: 76509 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/amd/onyx: use AMD SoC UART
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78267?usp=email ) Change subject: mb/amd/onyx: use AMD SoC UART ...................................................................... mb/amd/onyx: use AMD SoC UART Change-Id: I79ebbcc6a4a3a93e8437ef56aebdcf72f9a3e6ab Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78267 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/onyx/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/onyx/Kconfig b/src/mainboard/amd/onyx/Kconfig index 21c8c85..ebefa5c 100644 --- a/src/mainboard/amd/onyx/Kconfig +++ b/src/mainboard/amd/onyx/Kconfig @@ -4,6 +4,7 @@ def_bool y select SOC_AMD_GENOA select BOARD_ROMSIZE_KB_32768 + select AMD_SOC_CONSOLE_UART config FMDFILE default "src/mainboard/amd/onyx/board.fmd" -- To view, visit https://review.coreboot.org/c/coreboot/+/78267?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79ebbcc6a4a3a93e8437ef56aebdcf72f9a3e6ab Gerrit-Change-Number: 78267 Gerrit-PatchSet: 9 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/amd/genoa: Enable uart
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76507?usp=email ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Enable uart ...................................................................... soc/amd/genoa: Enable uart Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76507 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/uart.h A src/soc/amd/genoa/uart.c 5 files changed, 59 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index b4caa56..af4056a 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -19,6 +19,7 @@ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC + select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_USE_ESPI select X86_CUSTOM_BOOTMEDIA diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index a35146c..ef8f349 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -5,6 +5,7 @@ all-y += reset.c all-y += config.c all-y += gpio.c +all-y += uart.c bootblock-y += early_fch.c bootblock-y += aoac.c diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c index 8de43e2..e134f49 100644 --- a/src/soc/amd/genoa/early_fch.c +++ b/src/soc/amd/genoa/early_fch.c @@ -7,6 +7,7 @@ #include <amdblocks/pmlib.h> #include <amdblocks/uart.h> #include <soc/southbridge.h> +#include <soc/uart.h> /* Before console init */ void fch_pre_init(void) @@ -14,6 +15,14 @@ fch_enable_cf9_io(); enable_aoac_devices(); + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); configure_espi_with_mb_hook(); } diff --git a/src/soc/amd/genoa/include/soc/uart.h b/src/soc/amd/genoa/include/soc/uart.h new file mode 100644 index 0000000..ae8f118 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/uart.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_UART_H +#define AMD_GENOA_UART_H + +#include <types.h> + +void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ + +#endif /* AMD_GENOA_UART_H */ diff --git a/src/soc/amd/genoa/uart.c b/src/soc/amd/genoa/uart.c new file mode 100644 index 0000000..df8c54f --- /dev/null +++ b/src/soc/amd/genoa/uart.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <amdblocks/gpio.h> +#include <amdblocks/uart.h> +#include <commonlib/helpers.h> +#include <soc/aoac_defs.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/southbridge.h> +#include <soc/uart.h> +#include <types.h> + +static const struct soc_uart_ctrlr_info uart_info[] = { + [0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", { + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + } }, + [1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", { + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + PAD_NF(GPIO_142, UART1_TXD, PULL_NONE), + } }, + [2] = { APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", { + PAD_NF(GPIO_137, UART2_RXD, PULL_NONE), + PAD_NF(GPIO_135, UART2_TXD, PULL_NONE), + } }, +}; + +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; +} + +void clear_uart_legacy_config(void) +{ + write16((void *)FCH_LEGACY_UART_DECODE, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Gerrit-Change-Number: 76507 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/genoa: Add GPIO support
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78222?usp=email ) Change subject: soc/amd/genoa: Add GPIO support ...................................................................... soc/amd/genoa: Add GPIO support Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78222 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/gpio.c 3 files changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 2d57906..b4caa56 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -11,6 +11,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_LPC diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 2f7241d..a35146c 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -4,6 +4,7 @@ all-y += mmap_boot.c all-y += reset.c all-y += config.c +all-y += gpio.c bootblock-y += early_fch.c bootblock-y += aoac.c diff --git a/src/soc/amd/genoa/gpio.c b/src/soc/amd/genoa/gpio.c new file mode 100644 index 0000000..52cf272 --- /dev/null +++ b/src/soc/amd/genoa/gpio.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/gpio.h> +#include <soc/gpio.h> +#include <types.h> + +/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */ +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_21, GEVENT_5 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_14 }, + { GPIO_26, GEVENT_15 }, + { GPIO_76, GEVENT_11 }, + { GPIO_86, GEVENT_9 }, + { GPIO_89, GEVENT_0 }, + { GPIO_104, GEVENT_20 }, + { GPIO_105, GEVENT_22 }, + { GPIO_106, GEVENT_23 }, + { GPIO_115, GEVENT_1 }, + { GPIO_116, GEVENT_6 }, + { GPIO_129, GEVENT_17 }, +}; + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Gerrit-Change-Number: 78222 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/amd/genoa: Add SMI support
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78221?usp=email ) Change subject: soc/amd/genoa: Add SMI support ...................................................................... soc/amd/genoa: Add SMI support Add SMI definitions as per Genoa PPR Doc #55901 Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78221 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/genoa/Kconfig A src/soc/amd/genoa/include/soc/smi.h 2 files changed, 183 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 3044d71..2d57906 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -16,6 +16,7 @@ select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_USE_ESPI select X86_CUSTOM_BOOTMEDIA diff --git a/src/soc/amd/genoa/include/soc/smi.h b/src/soc/amd/genoa/include/soc/smi.h new file mode 100644 index 0000000..c9054c5 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/smi.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_GENOA_SMI_H +#define AMD_GENOA_SMI_H + +#include <types.h> + +#define SMI_GEVENTS 24 +#define SCIMAPS 64 /* 0..63 */ +#define SCI_GPES 32 +#define NUMBER_SMITYPES 157 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +/* SMI source and status */ +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_AGPIO115 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_AGPIO22 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_AGPIO21 5 +#define SMITYPE_G_AGPIO116 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_NMI_SYNC_FLOOD 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO76 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_SMERR_L 14 +#define SMITYPE_G_PCIE_RST1_L 15 +#define SMITYPE_G_ESPI_RSTOUT_L 16 +#define SMITYPE_G_ESPI_RSTIN_L 17 +#define SMITYPE_G_X48M_OUT 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO104 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPI105 22 +#define SMITYPE_G_AGPI106 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_AGPIO115) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_AGPIO22) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_AGPIO21) \ + | (1 << SMITYPE_G_AGPIO116) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_NMI_SYNC_FLOOD) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO76) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_SMERR_L) \ + | (1 << SMITYPE_G_PCIE_RST1_L) \ + | (1 << SMITYPE_G_ESPI_RSTOUT_L) \ + | (1 << SMITYPE_G_ESPI_RSTIN_L) \ + | (1 << SMITYPE_G_X48M_OUT) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO104) \ + | (1 << SMITYPE_G_PWR_BTN_L) \ + | (1 << SMITYPE_G_AGPI105) \ + | (1 << SMITYPE_G_AGPI106)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L2 32 +#define SMITYPE_PSP 33 +/* 34-35 Reserved */ +#define SMITYPE_ESPI_SCI_B 36 +#define SMITYPE_ESPI1_SYS_EVT_B 37 +#define SMITYPE_ESPI1_WAKE_PME 38 +#define SMITYPE_AZPME 39 +#define SMITYPE_USB_PD_I2C4 40 +#define SMITYPE_GPIO_CTL 41 +#define SMITYPE_ESPI1_SCI_B 42 +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +/* 59-63 Reserved */ +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +/* 67-71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +/* 145 Reserved */ +#define SMITYPE_ESPI_SMI 146 +#define SMITYPE_ESPI1_SMI 147 +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ + +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 + +#define SMI_MODE_MASK 0x03 + +#endif /* AMD_GENOA_SMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Gerrit-Change-Number: 78221 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[main]: soc/amd/genoa: Add GPIO definitions
by Felix Held (Code Review) 11 Oct '23

11 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78220?usp=email ) Change subject: soc/amd/genoa: Add GPIO definitions ...................................................................... soc/amd/genoa: Add GPIO definitions Add GPIO definitions as per Genoa PPR Doc #55901 Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78220 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/genoa/include/soc/gpio.h 1 file changed, 270 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/genoa/include/soc/gpio.h b/src/soc/amd/genoa/include/soc/gpio.h new file mode 100644 index 0000000..72d77c6 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/gpio.h @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_GPIO_H +#define AMD_GENOA_GPIO_H + +#define GPIO_DEVICE_NAME "AMDI0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include <soc/iomap.h> +#include <amdblocks/gpio.h> +#endif /* !__ACPI__ */ + +#include <amdblocks/gpio_defs.h> + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 267 + +/* Bank 0: GPIO_0 - GPIO_63 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_26 26 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_86 86 +#define GPIO_87 87 +#define GPIO_88 88 +#define GPIO_89 89 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_108 108 +#define GPIO_109 109 +#define GPIO_110 110 +#define GPIO_115 115 +#define GPIO_116 116 +#define GPIO_117 117 +#define GPIO_118 118 +#define GPIO_119 119 +#define GPIO_120 120 +#define GPIO_121 121 +#define GPIO_122 122 +#define GPIO_123 123 +#define GPIO_124 124 +#define GPIO_125 125 +#define GPIO_126 126 + +/* Bank 2: GPIO_128 - GPIO_191 */ +#define GPIO_129 129 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_133 133 +#define GPIO_134 134 +#define GPIO_135 135 +#define GPIO_136 136 +#define GPIO_137 137 +#define GPIO_138 138 +#define GPIO_139 139 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 +#define GPIO_149 149 +#define GPIO_150 150 +#define GPIO_151 151 +#define GPIO_152 152 + +/* remote GPIO bank: GPIO_256 - GPIO_271 */ +#define GPIO_256 256 +#define GPIO_257 257 +#define GPIO_258 258 +#define GPIO_259 259 +#define GPIO_260 260 +#define GPIO_261 261 +#define GPIO_262 262 +#define GPIO_263 263 +#define GPIO_264 264 +#define GPIO_265 265 +#define GPIO_266 266 + +/* IOMUX function names and values */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIO_PU1PD0 1 +#define GPIO_0_IOMUX_GPIOxx 2 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_SATA_ACT_L 1 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_DEVSLP0 1 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_DEVSLP1 1 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_12_IOMUX_PWRGD_OUT 0 +#define GPIO_12_IOMUX_GPIOxx 1 +#define GPIO_13_IOMUX_I2C4_SCL 0 +#define GPIO_13_IOMUX_CLK_48_24_0 1 +#define GPIO_13_IOMUX_GPIOxx 2 +#define GPIO_14_IOMUX_I2C4_SDA 0 +#define GPIO_14_IOMUX_S0A3 1 +#define GPIO_14_IOMUX_GPIOxx 2 +#define GPIO_16_IOMUX_USB_1O_OC_L 0 +#define GPIO_16_IOMUX_GPIOxx 1 +#define GPIO_17_IOMUX_USB11_OC_L 0 +#define GPIO_17_IOMUX_GPIOxx 1 +#define GPIO_19_IOMUX_I2C5_SCL 0 +#define GPIO_19_IOMUX_SMBUS1_SCL 1 +#define GPIO_19_IOMUX_GPIOxx 2 +#define GPIO_20_IOMUX_I2C5_SDA 0 +#define GPIO_20_IOMUX_SMBUS1_SDA 1 +#define GPIO_20_IOMUX_GPIOxx 2 +#define GPIO_21_IOMUX_GPIOxx 0 +#define GPIO_22_IOMUX_GPIOxx 0 +#define GPIO_23_IOMUX_ESPI_RST_OUT_L 0 +#define GPIO_23_IOMUX_GPIOxx 1 +#define GPIO_24_IOMUX_SMERR_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST1_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_ESPI_CLK2 0 +#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_75_IOMUX_ESPI_CLK1 0 +#define GPIO_75_IOMUX_GPIOxx 1 +#define GPIO_76_IOMUX_GPIOxx 0 +#define GPIO_76_IOMUX_SPI_TPM_CS_L 1 +#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0 +#define GPIO_87_IOMUX_GPIOxx 0 +#define GPIO_88_IOMUX_GPIOxx 0 +#define GPIO_89_IOMUX_GENINT_L 0 +#define GPIO_89_IOMUX_PM_INTR_L 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_104_IOMUX_GPIOxx 0 +#define GPIO_105_IOMUX_GPIOxx 0 +#define GPIO_106_IOMUX_GPIOxx 0 +#define GPIO_107_IOMUX_GPIOxx 0 +#define GPIO_108_IOMUX_ESPI0_ALERT_D1 0 +#define GPIO_108_IOMUX_GPIOxx 1 +#define GPIO_109_IOMUX_GPIOxx 0 +#define GPIO_110_IOMUX_ESPI1_ALERT_D1 0 +#define GPIO_110_IOMUX_GPIOxx 1 +#define GPIO_115_IOMUX_GPIOxx 0 +#define GPIO_115_IOMUX_CLK_REQ11_L 1 +#define GPIO_116_IOMUX_GPIOxx 0 +#define GPIO_116_IOMUX_CLK_REQ12_L 1 +#define GPIO_117_IOMUX_ESPI_CLK0 0 +#define GPIO_117_IOMUX_GPIOxx 1 +#define GPIO_118_IOMUX_SPI_CS0_L 0 +#define GPIO_118_IOMUX_GPIOxx 1 +#define GPIO_119_IOMUX_SPI_CS1_L 0 +#define GPIO_119_IOMUX_GPIOxx 1 +#define GPIO_120_IOMUX_ESPI0_DATA0 0 +#define GPIO_120_IOMUX_GPIOxx 1 +#define GPIO_121_IOMUX_ESPI0_DATA1 0 +#define GPIO_121_IOMUX_GPIOxx 1 +#define GPIO_122_IOMUX_ESPI0_DATA2 0 +#define GPIO_122_IOMUX_GPIOxx 1 +#define GPIO_123_IOMUX_ESPI0_DATA3 0 +#define GPIO_123_IOMUX_GPIOxx 1 +#define GPIO_124_IOMUX_ESPI_CS0_L 0 +#define GPIO_124_IOMUX_GPIOxx 1 +#define GPIO_125_IOMUX_ESPI_CS1_L 0 +#define GPIO_125_IOMUX_GPIOxx 1 +#define GPIO_126_IOMUX_SPI_CS2_L 0 +#define GPIO_126_IOMUX_GPIOxx 1 +#define GPIO_129_IOMUX_ESPI_RSTIN_L 0 +#define GPIO_129_IOMUX_KBRST_L 1 +#define GPIO_129_IOMUX_GPIOxx 2 +#define GPIO_131_IOMUX_ESPI1_DATA0 0 +#define GPIO_131_IOMUX_GPIOxx 1 +#define GPIO_132_IOMUX_ESPI1_DATA1 0 +#define GPIO_132_IOMUX_GPIOxx 1 +#define GPIO_133_IOMUX_ESPI1_DATA2 0 +#define GPIO_133_IOMUX_GPIOxx 1 +#define GPIO_134_IOMUX_ESPI1_DATA3 0 +#define GPIO_134_IOMUX_GPIOxx 1 +#define GPIO_135_IOMUX_UART0_CTS_L 0 +#define GPIO_135_IOMUX_UART2_TXD 1 +#define GPIO_135_IOMUX_GPIOxx 2 +#define GPIO_136_IOMUX_UART0_RXD 0 +#define GPIO_136_IOMUX_GPIOxx 1 +#define GPIO_137_IOMUX_UART0_RTS_L 0 +#define GPIO_137_IOMUX_UART2_RXD 1 +#define GPIO_137_IOMUX_GPIOxx 2 +#define GPIO_138_IOMUX_UART0_TXD 0 +#define GPIO_138_IOMUX_GPIOxx 1 +#define GPIO_139_IOMUX_UART0_INTR 0 +#define GPIO_139_IOMUX_GPIOxx 1 +#define GPIO_141_IOMUX_UART1_RXD 0 +#define GPIO_141_IOMUX_GPIOxx 1 +#define GPIO_142_IOMUX_UART1_TXD 0 +#define GPIO_142_IOMUX_GPIOxx 1 +#define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0 +#define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1 +#define GPIO_145_IOMUX_SMBUS0_SCL 2 +#define GPIO_145_IOMUX_GPIOxx 3 +#define GPIO_146_IOMUX_I3C0_SDA_SPD0_SDA 0 +#define GPIO_146_IOMUX_I2C0_SDA_SPD0_SDA 1 +#define GPIO_146_IOMUX_SMBUS0_SDA 2 +#define GPIO_146_IOMUX_GPIOxx 3 +#define GPIO_147_IOMUX_I3C1_SCL_SPD1_SCL 0 +#define GPIO_147_IOMUX_I2C1_SCL_SPD1_SCL 1 +#define GPIO_147_IOMUX_GPIOxx 2 +#define GPIO_148_IOMUX_I3C1_SDA_SPD1_SDA 0 +#define GPIO_148_IOMUX_I2C1_SDA_SPD1_SDA 1 +#define GPIO_148_IOMUX_GPIOxx 2 +#define GPIO_149_IOMUX_I3C2_SCL_SPD2_SCL 0 +#define GPIO_149_IOMUX_I2C2_SCL_SPD2_SCL 1 +#define GPIO_149_IOMUX_GPIOxx 2 +#define GPIO_150_IOMUX_I3C2_SDA_SPD2_SDA 0 +#define GPIO_150_IOMUX_I2C2_SDA_SPD2_SDA 1 +#define GPIO_150_IOMUX_GPIOxx 2 +#define GPIO_151_IOMUX_I3C3_SCL_SPD3_SCL 0 +#define GPIO_151_IOMUX_I2C3_SCL_SPD3_SCL 1 +#define GPIO_151_IOMUX_GPIOxx 2 +#define GPIO_152_IOMUX_I3C3_SDA_SPD3_SDA 0 +#define GPIO_152_IOMUX_I2C3_SDA_SPD3_SDA 1 +#define GPIO_152_IOMUX_GPIOxx 2 + +/* Remote GPIOs */ +#define GPIO_256_IOMUX_GPIOxx 0 +#define GPIO_256_IOMUX_SGPIO0_CLK 1 +#define GPIO_257_IOMUX_GPIOxx 0 +#define GPIO_257_IOMUX_SGPIO1_CLK 1 +#define GPIO_257_IOMUX_CLK_REQ01_L 2 +#define GPIO_258_IOMUX_GPIOxx 0 +#define GPIO_258_IOMUX_SGPIO2_CLK 1 +#define GPIO_258_IOMUX_CLK_REQ02_L 2 +#define GPIO_259_IOMUX_GPIOxx 0 +#define GPIO_259_IOMUX_SGPIO3_CLK 1 +#define GPIO_260_IOMUX_SGPIO_DATAOUT 0 +#define GPIO_260_IOMUX_GPIOxx 1 +#define GPIO_261_IOMUX_SGPIO_LOAD 0 +#define GPIO_261_IOMUX_GPIOxx 1 +#define GPIO_262_IOMUX_GPIOxx 0 +#define GPIO_263_IOMUX_GPIOxx 0 +#define GPIO_264_IOMUX_USB00_OC_L 0 +#define GPIO_264_IOMUX_GPIOxx 1 +#define GPIO_265_IOMUX_USB01_OC_L 0 +#define GPIO_265_IOMUX_GPIOxx 1 +#define GPIO_266_IOMUX_PCIE_RST0_L 0 +#define GPIO_266_IOMUX_GPIOxx 1 + +#endif /* AMD_GENOA_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Gerrit-Change-Number: 78220 Gerrit-PatchSet: 9 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/intel/mtlrvp: Add new MTL-P board variant for PD solution
by Jay Patel (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Bernardo Perez Priego, Brandon Breitenstein, Paul Menzel, Tanu Malhotra, Vijay P Hiremath. Hello Bernardo Perez Priego, Brandon Breitenstein, Tanu Malhotra, Vijay P Hiremath, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78282?usp=email to look at the new patch set (#4). Change subject: mb/intel/mtlrvp: Add new MTL-P board variant for PD solution ...................................................................... mb/intel/mtlrvp: Add new MTL-P board variant for PD solution This patch adds new board variant to enable PD chip based type-C solution for MTL-RVP. Reshuffles Type-C related devicetree code since the mtlrvp_pd variant supports 2 type-C ports while the other variants support 4. BUG=b:303839908 BRANCH=none TEST=check if you can observe MTLRVP PD solution option as part of make menuconfig. Able to boot to ChromeOS with PD solution. Change-Id: I8c98f08e143ac4ea620aca049e22f4e1e2f97e9e Signed-off-by: Jay Patel <jay2.patel(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Kconfig.name M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/mtlrvp/variants/mtlrvp_p/overridetree.cb M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_pd/overridetree.cb 6 files changed, 76 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/78282/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c98f08e143ac4ea620aca049e22f4e1e2f97e9e Gerrit-Change-Number: 78282 Gerrit-PatchSet: 4 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2023