coreboot-gerrit October 2023

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[XL] Change in coreboot[main]: lib/jpeg: Replace decoder with Wuffs' implementation
by Nigel Tao (Code Review) 12 Oct '23

12 Oct '23

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[XL] Change in coreboot[main]: lib/jpeg: Replace decoder with Wuffs' implementation
by Nigel Tao (Code Review) 12 Oct '23

12 Oct '23

1 0

[XL] Change in coreboot[main]: lib/jpeg: Replace decoder with Wuffs' implementation
by Nigel Tao (Code Review) 12 Oct '23

12 Oct '23

1 0

[XL] Change in coreboot[main]: lib/jpeg: Replace decoder with Wuffs' implementation
by Nigel Tao (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Martin L Roth, Patrick Georgi, Tim Wawrzynczak. Nigel Tao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78271?usp=email ) Change subject: lib/jpeg: Replace decoder with Wuffs' implementation ...................................................................... Patch Set 2: (6 comments) Patchset: PS2: I dropped some drive-by comments. Feel free to CC me on future Wuffs-related coreboot reviews. File src/lib/jpeg.c: https://review.coreboot.org/c/coreboot/+/78271/comment/c7ee49d3_3a824457 : PS2, Line 9: #include <stdint.h> FYI, I don't know how strict you coreboot folks are about #include style, but this is possibly unnecessary, because `#include "../vendorcode/wuffs/wuffs-v0.4.c"` will pull in `stdint.h`. https://review.coreboot.org/c/coreboot/+/78271/comment/2ce117d3_87a08ee2 : PS2, Line 97: uint64_t workbuf_len_min_incl = wuffs_jpeg__decoder__workbuf_len(&dec).min_incl; etc.min_incl (at the end of the statement) is fine and will work. But FYI, using max_incl instead turns the knob from "optimize for less memory usage" to "optimize for more decode speed". That's in theory. In practice, as of version 0.4 today, the minimum and maximum settings are the same number. But versions 0.4 in the future might implement multiple algorithms and let the caller configure. https://review.coreboot.org/c/coreboot/+/78271/comment/58b94e18_929ca369 : PS2, Line 99: if (workbuf_array == 0) { ``` if ((workbuf_array == 0) && workbuf_len_min_incl) { ``` might be more robust, in case a future Wuffs version drops the minimum work buffer memory usage down to zero. https://review.coreboot.org/c/coreboot/+/78271/comment/6b9d61a4_1430854e : PS2, Line 107: if (status.repr) { I think you want a `free(workbuf_array)` before this line, as the Wuffs JPEG decoder no longer needs the work buffer, but I don't know coreboot's malloc/free at all (e.g. what's a ramstage). https://review.coreboot.org/c/coreboot/+/78271/comment/9d4901ff_dfb11605 : PS2, Line 108: return JPEG_DECODE_FAILED; FYI, if you want separate error codes to distinguish e.g. "invalid argument" from "invalid JPEG" from "unsupported JPEG" (e.g. strictly speaking, the JPEG spec allows for 12-bit precision, instead of 8-bit, but these are very, very rare and many JPEG libraries, including Wuffs, do not support them), then: A `wuffs_base__status` is just a `const char*`, wrapped in a struct (so that, in C++, it can have syntactic-sugar methods): ``` typedef struct wuffs_base__status__struct { const char* repr; #ifdef __cplusplus // etc #endif // __cplusplus } wuffs_base__status; ``` The `const char*` is always a C string literal and can be compared by `==`, not just by `strcmp`. Wuffs' general 'base' errors and JPEG-specific errors have declarations like this: ``` // This is an excerpt. For a full list: // grep ^extern.const.char.wuffs_.*__error_ wuffs-v0.4.c extern const char wuffs_base__error__bad_argument[]; extern const char wuffs_base__error__bad_receiver[]; extern const char wuffs_base__error__bad_wuffs_version[]; extern const char wuffs_base__error__unsupported_image_dimension[]; // etc extern const char wuffs_jpeg__error__bad_dht_marker[]; extern const char wuffs_jpeg__error__bad_dqt_marker[]; extern const char wuffs_jpeg__error__bad_dri_marker[]; extern const char wuffs_jpeg__error__bad_sof_marker[]; extern const char wuffs_jpeg__error__bad_sos_marker[]; extern const char wuffs_jpeg__error__missing_huffman_table[]; extern const char wuffs_jpeg__error__missing_quantization_table[]; extern const char wuffs_jpeg__error__truncated_input[]; extern const char wuffs_jpeg__error__unsupported_precision_12_bits[]; extern const char wuffs_jpeg__error__unsupported_precision_16_bits[]; extern const char wuffs_jpeg__error__unsupported_precision[]; extern const char wuffs_jpeg__error__unsupported_scan_count[]; ``` A NULL `const char*` means OK. So, here, you could do something like ``` if (!status.repr) { // No-op. } else if (status.repr == wuffs_jpeg__error__truncated_input) { return SOME_SPECIFIC_ERROR_CODE; } else if ((status.repr == wuffs_jpeg__error__unsupported_precision_12_bits) || (status.repr == wuffs_jpeg__error__unsupported_precision_16_bits)) { return SOME_OTHER_SPECIFIC_ERROR_CODE; } else { return SOME_GENERAL_ERROR_CODE; } ``` Again, that's all if you care to distinguish different errors. If you don't care, `return JPEG_DECODE_FAILED` is fine. --- Separately, if your `printk` can handle `%s` instead of `%d`, your `jpeg_decode` function could return `const char*` instead of `int`. The actual error string definitions look like this: ``` const char wuffs_jpeg__error__unsupported_precision_12_bits[] = "#jpeg: unsupported precision (12 bits)"; ``` and the code here changes from ``` if (status.repr) { return JPEG_DECODE_FAILED; } return 0; ``` to ``` return status.repr; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82 Gerrit-Change-Number: 78271 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nigel Tao <nigeltao(a)golang.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 12 Oct 2023 00:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: allow to configure slp-s0 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Lance Zhao, Paul Menzel, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: allow to configure slp-s0 residency counter frequency in LPIT table ...................................................................... Patch Set 16: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78164/comment/6a3d32c3_362a9233 : PS14, Line 7: configurable slp-s0 residency counter frequency in LPIT table > done Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 16 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 22:53:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: allow to configure slp-s0 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Lance Zhao, Paul Menzel, Subrata Banik, Tarun, Tim Wawrzynczak. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: allow to configure slp-s0 residency counter frequency in LPIT table ...................................................................... Patch Set 15: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78164/comment/a410bab5_3e0db767 : PS14, Line 7: configurable slp-s0 residency counter frequency in LPIT table > Not solved yet. done -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 15 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 22:53:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: allow to configure slp-s0 residency counter frequency in LPIT table
by Sukumar Ghorai (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Lance Zhao, Subrata Banik, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Hello Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Paul Menzel, Subrata Banik, Tarun, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78164?usp=email to look at the new patch set (#16). Change subject: allow to configure slp-s0 residency counter frequency in LPIT table ...................................................................... allow to configure slp-s0 residency counter frequency in LPIT table Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_… System sleep time (SLP_S0 signal asserted) is measured in ticks, varies in every platform and based on PMC clock. BUG=b:300440936 TEST=check kernel cpuidle sysfs for non-zero residency after s0ix cycle and both must match cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/include/acpi/acpi.h 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78164/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 16 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ
by Nick Vaccaro (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Subrata Banik. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78318?usp=email ) Change subject: mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1 Gerrit-Change-Number: 78318 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 22:33:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78009?usp=email ) Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... Patch Set 11: (3 comments) File src/mainboard/google/brox/Kconfig: https://review.coreboot.org/c/coreboot/+/78009/comment/d4e9aace_e6b8d31c : PS9, Line 84: BOARD_GOOGLE_BASEBOARD_HADES > You can get rid of checks for hades, hades has been deprecated and wouldn't be part of the brox fami […] Done https://review.coreboot.org/c/coreboot/+/78009/comment/484623a0_56592fb3 : PS9, Line 85: BOARD_GOOGLE_BASEBOARD_HADES > same Done https://review.coreboot.org/c/coreboot/+/78009/comment/c5f100d4_8b851764 : PS9, Line 154: BOARD_GOOGLE_PIRRHA > Is pirrha a Brox variant? If not, this check should be deleted. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 11 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 22:29:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 12 Oct '23

12 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel. Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78009?usp=email to look at the new patch set (#11). Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... mb/google/brox: Create new Brox baseboard This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/brox/Kconfig A src/mainboard/google/brox/Kconfig.name A src/mainboard/google/brox/Makefile.inc A src/mainboard/google/brox/acpi/gps.asl A src/mainboard/google/brox/acpi/gpu_defines.h A src/mainboard/google/brox/acpi/gpu_ec.asl A src/mainboard/google/brox/acpi/gpu_top.asl A src/mainboard/google/brox/acpi/nbci.asl A src/mainboard/google/brox/acpi/nvjt.asl A src/mainboard/google/brox/acpi/nvop.asl A src/mainboard/google/brox/acpi/nvpcf.asl A src/mainboard/google/brox/acpi/peg.asl A src/mainboard/google/brox/acpi/power.asl A src/mainboard/google/brox/acpi/utility.asl A src/mainboard/google/brox/board_info.txt A src/mainboard/google/brox/bootblock.c A src/mainboard/google/brox/chromeos.c A src/mainboard/google/brox/chromeos.fmd A src/mainboard/google/brox/dsdt.asl A src/mainboard/google/brox/ec.c A src/mainboard/google/brox/mainboard.c A src/mainboard/google/brox/romstage.c A src/mainboard/google/brox/smihandler.c A src/mainboard/google/brox/spd/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb A src/mainboard/google/brox/variants/baseboard/brox/gma-mainboard.ads A src/mainboard/google/brox/variants/baseboard/brox/gpio.c A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h A src/mainboard/google/brox/variants/baseboard/brox/memory.c A src/mainboard/google/brox/variants/baseboard/brox/ramstage.c A src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brox/variants/brox/Makefile.inc A src/mainboard/google/brox/variants/brox/data.vbt A src/mainboard/google/brox/variants/brox/fw_config.c A src/mainboard/google/brox/variants/brox/gpio.c A src/mainboard/google/brox/variants/brox/include/variant/ec.h A src/mainboard/google/brox/variants/brox/include/variant/gpio.h A src/mainboard/google/brox/variants/brox/memory/Makefile.inc A src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt A src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt A src/mainboard/google/brox/variants/brox/overridetree.cb A src/mainboard/google/brox/variants/brox/ramstage.c A src/mainboard/google/brox/variants/brox/variant.c A src/mainboard/google/brox/wwan_power.asl 46 files changed, 2,854 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78009/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 11 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2023