coreboot-gerrit January 2023

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[M] Change in coreboot[master]: soc/intel/meteorlake: provide a list of D-states to enter LPM
by Kapil Porwal (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71644 ) Change subject: soc/intel/meteorlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/meteorlake/acpi.c: https://review.coreboot.org/c/coreboot/+/71644/comment/6b45fafa_88b42063 PS7, Line 212: { PCI_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, : { PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, Duplicates with different device sleep state (D3 vs D0). -- To view, visit https://review.coreboot.org/c/coreboot/+/71644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8 Gerrit-Change-Number: 71644 Gerrit-PatchSet: 7 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 09:30:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: use i2c1 for TPM for omnigul
by Jamie Chen (Code Review) 05 Jan '23

05 Jan '23

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71703 ) Change subject: mb/google/brya/var/omnigul: use i2c1 for TPM for omnigul ...................................................................... mb/google/brya/var/omnigul: use i2c1 for TPM for omnigul This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the omnigul variant. BUG=NA TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/71703/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9f0c223..15de567 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -153,6 +153,7 @@ default 0x1 if BOARD_GOOGLE_GLADIOS default 0x1 if BOARD_GOOGLE_MARASOV default 0x1 if BOARD_GOOGLE_GAELIN + default 0x1 if BOARD_GOOGLE_omnigul config DRIVER_TPM_I2C_ADDR hex -- To view, visit https://review.coreboot.org/c/coreboot/+/71703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Gerrit-Change-Number: 71703 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: use RPL FSP headers
by Jamie Chen (Code Review) 05 Jan '23

05 Jan '23

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71702 ) Change subject: mb/google/brya/var/omnigul: use RPL FSP headers ...................................................................... mb/google/brya/var/omnigul: use RPL FSP headers To support an RPL SKU on omnigul, omnigul must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL FSP headers for omnigul. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85 Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/71702/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index e5cfe3a..37610f3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -321,3 +321,4 @@ config BOARD_GOOGLE_OMNIGUL bool "-> Omnigul" select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/71702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 Gerrit-Change-Number: 71702 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] mb/amd/birman: Move EC FW to FMAP
by Bao Zheng (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Jason Glenesk, ritul guru, Fred Reitberger, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70695 ) Change subject: [WIP] mb/amd/birman: Move EC FW to FMAP ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: https://review.coreboot.org/c/coreboot/+/70778 This merged CL splits the EFS header and body. The gap is for the EC FW. -- To view, visit https://review.coreboot.org/c/coreboot/+/70695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b19d92043790b10acd20fbfdf394d5bd67b8295 Gerrit-Change-Number: 70695 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 05 Jan 2023 08:44:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add common function to disable LT memory lock
by Kapil Porwal (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Jérémy Compostella, Angel Pons. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71655 ) Change subject: soc/intel/common: Add common function to disable LT memory lock ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71655/comment/41fc567e_edf98397 PS4, Line 9: 4 `6` -- To view, visit https://review.coreboot.org/c/coreboot/+/71655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic666919ed51f683c9a1ef0b7ba061cd2949faf1e Gerrit-Change-Number: 71655 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 08:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel: Remove dummy _SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 05 Jan '23

05 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71701 ) Change subject: soc/intel: Remove dummy _SPECIFIC_OPTIONS ...................................................................... soc/intel: Remove dummy _SPECIFIC_OPTIONS Change-Id: I7cfdc477e8aec53bdfcfd4498e2dea83a7696dd0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig 17 files changed, 206 insertions(+), 242 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/71701/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 9d950a7..b7f32f0 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -1,50 +1,5 @@ config SOC_INTEL_ALDERLAKE bool - help - Intel Alderlake support. Mainboards should specify the PCH - type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead - of selecting this option directly. - -config SOC_INTEL_RAPTORLAKE - bool - select X86_INIT_NEED_1_SIPI - help - Intel Raptorlake support. Mainboards using RPL should select - SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. - -config SOC_INTEL_ALDERLAKE_PCH_M - bool - select SOC_INTEL_ALDERLAKE - help - Choose this option if your mainboard has a PCH-M chipset. - -config SOC_INTEL_ALDERLAKE_PCH_N - bool - select SOC_INTEL_ALDERLAKE - select MICROCODE_BLOB_UNDISCLOSED - help - Choose this option if your mainboard has a PCH-N chipset. - -config SOC_INTEL_ALDERLAKE_PCH_P - bool - select SOC_INTEL_ALDERLAKE - select HAVE_INTEL_FSP_REPO - select PLATFORM_USES_FSP2_3 - help - Choose this option if your mainboard has a PCH-P chipset. - -config SOC_INTEL_ALDERLAKE_PCH_S - bool - select SOC_INTEL_ALDERLAKE - select HAVE_INTEL_FSP_REPO - select PLATFORM_USES_FSP2_3 - help - Choose this option if your mainboard has a PCH-S chipset. - -if SOC_INTEL_ALDERLAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_ADL_IPU_ES_SUPPORT select ARCH_X86 @@ -127,6 +82,48 @@ select UDELAY_TSC select UDK_202005_BINDING select VBOOT_LIB + help + Intel Alderlake support. Mainboards should specify the PCH + type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead + of selecting this option directly. + +config SOC_INTEL_RAPTORLAKE + bool + select X86_INIT_NEED_1_SIPI + help + Intel Raptorlake support. Mainboards using RPL should select + SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. + +config SOC_INTEL_ALDERLAKE_PCH_M + bool + select SOC_INTEL_ALDERLAKE + help + Choose this option if your mainboard has a PCH-M chipset. + +config SOC_INTEL_ALDERLAKE_PCH_N + bool + select SOC_INTEL_ALDERLAKE + select MICROCODE_BLOB_UNDISCLOSED + help + Choose this option if your mainboard has a PCH-N chipset. + +config SOC_INTEL_ALDERLAKE_PCH_P + bool + select SOC_INTEL_ALDERLAKE + select HAVE_INTEL_FSP_REPO + select PLATFORM_USES_FSP2_3 + help + Choose this option if your mainboard has a PCH-P chipset. + +config SOC_INTEL_ALDERLAKE_PCH_S + bool + select SOC_INTEL_ALDERLAKE + select HAVE_INTEL_FSP_REPO + select PLATFORM_USES_FSP2_3 + help + Choose this option if your mainboard has a PCH-S chipset. + +if SOC_INTEL_ALDERLAKE config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT bool diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 395d7aa6..39d1a8e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -1,27 +1,6 @@ config SOC_INTEL_APOLLOLAKE bool select INTEL_CAR_CQOS - help - Intel Apollolake support - -config SOC_INTEL_GEMINILAKE - bool - default n - select SOC_INTEL_APOLLOLAKE - select SOC_INTEL_COMMON_BLOCK_CNVI - select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_SGX - select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 - select IDT_IN_EVERY_STAGE - select PAGING_IN_CACHE_AS_RAM - select INTEL_CAR_NEM - help - Intel GLK support - -if SOC_INTEL_APOLLOLAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NO_PCAT_8259 select ARCH_X86 @@ -101,6 +80,24 @@ # This SoC does not map SPI flash like many previous SoC. Therefore we # provide a custom media driver that facilitates mapping select X86_CUSTOM_BOOTMEDIA + help + Intel Apollolake support + +config SOC_INTEL_GEMINILAKE + bool + default n + select SOC_INTEL_APOLLOLAKE + select SOC_INTEL_COMMON_BLOCK_CNVI + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_SGX + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select IDT_IN_EVERY_STAGE + select PAGING_IN_CACHE_AS_RAM + select INTEL_CAR_NEM + help + Intel GLK support + +if SOC_INTEL_APOLLOLAKE config SKIP_CSE_RBP bool diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5ecfe3e..50b83bf 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -1,12 +1,5 @@ config SOC_INTEL_BAYTRAIL bool - help - Bay Trail M/D part support. - -if SOC_INTEL_BAYTRAIL - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES @@ -35,6 +28,10 @@ select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR select TCO_SPACE_NOT_YET_SPLIT + help + Bay Trail M/D part support. + +if SOC_INTEL_BAYTRAIL config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4d3d4df..4a209f6 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -1,12 +1,5 @@ config SOC_INTEL_BRASWELL bool - help - Braswell M/D part support. - -if SOC_INTEL_BRASWELL - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -42,6 +35,10 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_CBFS_MCACHE select TCO_SPACE_NOT_YET_SPLIT + help + Braswell M/D part support. + +if SOC_INTEL_BRASWELL config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 3878f14..e5784c5 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -1,18 +1,15 @@ config SOC_INTEL_BROADWELL bool - help - Intel Broadwell and Haswell ULT support. - -if SOC_INTEL_BROADWELL - -config SOC_SPECIFIC_OPTIONS - def_bool y select CACHE_MRC_SETTINGS select CPU_INTEL_HASWELL select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT select REG_SCRIPT select TCO_SPACE_NOT_YET_SPLIT + help + Intel Broadwell and Haswell ULT support. + +if SOC_INTEL_BROADWELL config BROADWELL_LPDDR3 bool diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 5a80d32..9674edf 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -1,9 +1,6 @@ config INTEL_LYNXPOINT_LP bool default y if SOC_INTEL_BROADWELL - -config PCH_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT @@ -25,6 +22,8 @@ select SPI_FLASH select TCO_SPACE_NOT_YET_SPLIT +if INTEL_LYNXPOINT_LP + config EHCI_BAR hex default 0xd8000000 @@ -74,3 +73,5 @@ Disable and hide the ME PCI interface during finalize stage of boot. This will prevent the OS (and userspace apps) from interacting with the ME via the PCI interface after boot. + +endif diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 16a3cbd..9a4d5dc 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -1,56 +1,5 @@ config SOC_INTEL_CANNONLAKE_BASE bool - -config SOC_INTEL_COFFEELAKE - bool - select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_EXP_X86_64_SUPPORT - select HAVE_INTEL_FSP_REPO - select HECI_DISABLE_USING_SMM - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - -config SOC_INTEL_WHISKEYLAKE - bool - select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_INTEL_FSP_REPO - select HECI_DISABLE_USING_SMM - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - -config SOC_INTEL_COMETLAKE - bool - select SOC_INTEL_CANNONLAKE_BASE - select FSP_USES_CB_STACK - select HAVE_INTEL_FSP_REPO - select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC - select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU - -config SOC_INTEL_COMETLAKE_1 - bool - select SOC_INTEL_COMETLAKE - -config SOC_INTEL_COMETLAKE_2 - bool - select SOC_INTEL_COMETLAKE - -config SOC_INTEL_COMETLAKE_S - bool - select SOC_INTEL_COMETLAKE - -config SOC_INTEL_COMETLAKE_V - bool - select SOC_INTEL_COMETLAKE - -config SOC_INTEL_CANNONLAKE_PCH_H - bool - -if SOC_INTEL_CANNONLAKE_BASE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_X86 @@ -119,6 +68,54 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE +config SOC_INTEL_COFFEELAKE + bool + select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK + select HAVE_EXP_X86_64_SUPPORT + select HAVE_INTEL_FSP_REPO + select HECI_DISABLE_USING_SMM + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + +config SOC_INTEL_WHISKEYLAKE + bool + select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK + select HAVE_INTEL_FSP_REPO + select HECI_DISABLE_USING_SMM + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + +config SOC_INTEL_COMETLAKE + bool + select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK + select HAVE_INTEL_FSP_REPO + select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + +config SOC_INTEL_COMETLAKE_1 + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_2 + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_S + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_V + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_CANNONLAKE_PCH_H + bool + +if SOC_INTEL_CANNONLAKE_BASE + config MAX_CPUS int default 20 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index dcf9a5f..f8d3a75 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -2,17 +2,6 @@ config SOC_INTEL_DENVERTON_NS bool - help - Intel Denverton-NS SoC support - -if SOC_INTEL_DENVERTON_NS - -config CPU_INTEL_NUM_FIT_ENTRIES - int - default 1 - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS @@ -51,6 +40,15 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + help + Intel Denverton-NS SoC support + +if SOC_INTEL_DENVERTON_NS + +config CPU_INTEL_NUM_FIT_ENTRIES + int + default 1 + config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 8e3dc11..531285e 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -1,12 +1,5 @@ config SOC_INTEL_ELKHARTLAKE bool - help - Intel Elkhartlake support - -if SOC_INTEL_ELKHARTLAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -67,6 +60,10 @@ select UDK_202005_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR + help + Intel Elkhartlake support + +if SOC_INTEL_ELKHARTLAKE config MAX_CPUS int diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index aca73fa..92182f5 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -1,12 +1,5 @@ config SOC_INTEL_ICELAKE bool - help - Intel Icelake support - -if SOC_INTEL_ICELAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -67,6 +60,10 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + help + Intel Icelake support + +if SOC_INTEL_ICELAKE config DISABLE_HECI1_AT_PRE_BOOT default y if MAINBOARD_HAS_CHROMEOS diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 4ae21b8..6dde269 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,12 +1,5 @@ config SOC_INTEL_JASPERLAKE bool - help - Intel Jasperlake support - -if SOC_INTEL_JASPERLAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -73,6 +66,10 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + help + Intel Jasperlake support + +if SOC_INTEL_JASPERLAKE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 4d69566..b6c39eb 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -1,12 +1,5 @@ config SOC_INTEL_METEORLAKE bool - help - Intel Meteorlake support - -if SOC_INTEL_METEORLAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -92,6 +85,10 @@ select UDELAY_TSC select UDK_202111_BINDING select X86_INIT_NEED_1_SIPI + help + Intel Meteorlake support + +if SOC_INTEL_METEORLAKE config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT bool diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 58f01da..51e31ce 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -2,13 +2,6 @@ config SOC_INTEL_QUARK bool - help - Intel Quark support - -if SOC_INTEL_QUARK - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_NO_MADT select ARCH_X86 select NO_ECAM_MMCONF_SUPPORT @@ -27,6 +20,10 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select USE_MARCH_586 + help + Intel Quark support + +if SOC_INTEL_QUARK ##### # Debug serial output diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e15af04..d6a11363e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -1,26 +1,5 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE bool - -config SOC_INTEL_SKYLAKE - bool - select SOC_INTEL_COMMON_SKYLAKE_BASE - -config SOC_INTEL_KABYLAKE - bool - select SOC_INTEL_COMMON_SKYLAKE_BASE - -config SOC_INTEL_SKYLAKE_LGA1151_V2 - bool - select PLATFORM_USES_FSP2_1 - select SOC_INTEL_COMMON_SKYLAKE_BASE - select SKYLAKE_SOC_PCH_H - help - Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH - -if SOC_INTEL_COMMON_SKYLAKE_BASE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_X86 @@ -92,6 +71,24 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE +config SOC_INTEL_SKYLAKE + bool + select SOC_INTEL_COMMON_SKYLAKE_BASE + +config SOC_INTEL_KABYLAKE + bool + select SOC_INTEL_COMMON_SKYLAKE_BASE + +config SOC_INTEL_SKYLAKE_LGA1151_V2 + bool + select PLATFORM_USES_FSP2_1 + select SOC_INTEL_COMMON_SKYLAKE_BASE + select SKYLAKE_SOC_PCH_H + help + Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH + +if SOC_INTEL_COMMON_SKYLAKE_BASE + config MAX_HECI_DEVICES int default 5 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index bcf4a82..438cfd1 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,15 +1,5 @@ config SOC_INTEL_TIGERLAKE bool - help - Intel Tigerlake support - -config SOC_INTEL_TIGERLAKE_PCH_H - bool - -if SOC_INTEL_TIGERLAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -93,6 +83,13 @@ select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 + help + Intel Tigerlake support + +config SOC_INTEL_TIGERLAKE_PCH_H + bool + +if SOC_INTEL_TIGERLAKE config MAX_CPUS int diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 91b1569..2bd320f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -6,26 +6,6 @@ config XEON_SP_COMMON_BASE bool - -config SOC_INTEL_SKYLAKE_SP - bool - select XEON_SP_COMMON_BASE - select PLATFORM_USES_FSP2_0 - help - Intel Skylake-SP support - -config SOC_INTEL_COOPERLAKE_SP - bool - select XEON_SP_COMMON_BASE - select PLATFORM_USES_FSP2_2 - select CACHE_MRC_SETTINGS - help - Intel Cooper Lake-SP support - -if XEON_SP_COMMON_BASE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES @@ -62,6 +42,24 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE +config SOC_INTEL_SKYLAKE_SP + bool + select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_0 + help + Intel Skylake-SP support + +config SOC_INTEL_COOPERLAKE_SP + bool + select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_2 + select CACHE_MRC_SETTINGS + select HAVE_INTEL_FSP_REPO + help + Intel Cooper Lake-SP support + +if XEON_SP_COMMON_BASE + config MAINBOARD_USES_FSP2_0 bool default y diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index aa344ce..c3bcc94 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,10 +2,6 @@ if SOC_INTEL_COOPERLAKE_SP -config SOC_SPECIFIC_OPTIONS - def_bool y - select HAVE_INTEL_FSP_REPO - config FSP_HEADER_PATH default "3rdparty/fsp/CedarIslandFspBinPkg/Include" -- To view, visit https://review.coreboot.org/c/coreboot/+/71701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfdc477e8aec53bdfcfd4498e2dea83a7696dd0 Gerrit-Change-Number: 71701 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa: Disable stage cache
by Eric Lai (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Reka Norman. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71677 ) Change subject: mb/google/nissa: Disable stage cache ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Gerrit-Change-Number: 71677 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Jan 2023 07:18:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/example: Remove dummy SOC_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Nico Huber. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71700 ) Change subject: soc/example: Remove dummy SOC_SPECIFIC_OPTIONS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/71700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f512d77218e9053968f85cd8f188499e711ecf1 Gerrit-Change-Number: 71700 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 05 Jan 2023 06:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/example: Remove dummy SOC_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 05 Jan '23

05 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71700 ) Change subject: soc/example: Remove dummy SOC_SPECIFIC_OPTIONS ...................................................................... soc/example: Remove dummy SOC_SPECIFIC_OPTIONS Change-Id: I6f512d77218e9053968f85cd8f188499e711ecf1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/example/min86/Kconfig 1 file changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/71700/1 diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index d176752..12a13e5 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -1,5 +1,9 @@ config SOC_EXAMPLE_MIN86 bool + select ARCH_X86 + select NO_MONOTONIC_TIMER + select NO_ECAM_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE help This example SoC code along with the example/min86 mainboard should serve as a minimal example how a buildable x86 SoC code @@ -12,13 +16,6 @@ if SOC_EXAMPLE_MIN86 -config SOC_SPECIFIC_OPTIONS - def_bool y - select ARCH_X86 - select NO_MONOTONIC_TIMER - select NO_ECAM_MMCONF_SUPPORT - select UNKNOWN_TSC_RATE - config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld default 0x100 -- To view, visit https://review.coreboot.org/c/coreboot/+/71700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f512d77218e9053968f85cd8f188499e711ecf1 Gerrit-Change-Number: 71700 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd: Remove dummy SOC_SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 05 Jan '23

05 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71679 ) Change subject: soc/amd: Remove dummy SOC_SPECIFIC_OPTIONS ...................................................................... soc/amd: Remove dummy SOC_SPECIFIC_OPTIONS Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/mendocino/Kconfig M src/soc/amd/morgana/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 6 files changed, 45 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/71679/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 30e3e73..0de2ab7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -2,13 +2,6 @@ config SOC_AMD_CEZANNE bool - help - AMD Cezanne support - -if SOC_AMD_CEZANNE - -config SOC_SPECIFIC_OPTIONS - def_bool y select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -83,6 +76,10 @@ select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI + help + AMD Cezanne support + +if SOC_AMD_CEZANNE config CHIPSET_DEVICETREE string diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 5bf1d5f..f4f49b9 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -5,13 +5,6 @@ config SOC_AMD_GLINDA bool - help - AMD Glinda support - -if SOC_AMD_GLINDA - -config SOC_SPECIFIC_OPTIONS - def_bool y select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -88,6 +81,10 @@ select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI + help + AMD Glinda support + +if SOC_AMD_GLINDA config CHIPSET_DEVICETREE string diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 142165c..4dd0eaf 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -4,24 +4,6 @@ config SOC_AMD_REMBRANDT_BASE bool - -config SOC_AMD_MENDOCINO - bool - select SOC_AMD_REMBRANDT_BASE - help - AMD Mendocino support - -config SOC_AMD_REMBRANDT - bool - select SOC_AMD_REMBRANDT_BASE - help - AMD Rembrandt support - - -if SOC_AMD_REMBRANDT_BASE - -config SOC_SPECIFIC_OPTIONS - def_bool y select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -103,6 +85,21 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI +config SOC_AMD_MENDOCINO + bool + select SOC_AMD_REMBRANDT_BASE + help + AMD Mendocino support + +config SOC_AMD_REMBRANDT + bool + select SOC_AMD_REMBRANDT_BASE + help + AMD Rembrandt support + + +if SOC_AMD_REMBRANDT_BASE + config CHIPSET_DEVICETREE string default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index 7765f92..1106a46 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -5,13 +5,6 @@ config SOC_AMD_MORGANA bool - help - AMD Morgana support - -if SOC_AMD_MORGANA - -config SOC_SPECIFIC_OPTIONS - def_bool y select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -88,6 +81,10 @@ select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI + help + AMD Morgana support + +if SOC_AMD_MORGANA config CHIPSET_DEVICETREE string diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 765ac4c..b18868d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -2,13 +2,6 @@ config SOC_AMD_PICASSO bool - help - AMD Picasso support - -if SOC_AMD_PICASSO - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_SOC_NVS select ADD_FSP_BINARIES if USE_AMD_BLOBS select ARCH_X86 @@ -76,6 +69,10 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI select HAVE_EXP_X86_64_SUPPORT + help + AMD Picasso support + +if SOC_AMD_PICASSO config CHIPSET_DEVICETREE string diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 01800c1..12d66c4 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -2,13 +2,6 @@ config SOC_AMD_STONEYRIDGE bool - help - AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. - -if SOC_AMD_STONEYRIDGE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -51,6 +44,10 @@ select TSC_SYNC_LFENCE select USE_DDR4 select X86_AMD_FIXED_MTRRS + help + AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. + +if SOC_AMD_STONEYRIDGE config AMD_APU_STONEYRIDGE bool -- To view, visit https://review.coreboot.org/c/coreboot/+/71679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Gerrit-Change-Number: 71679 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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