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Change subject: mb/google/nissa: Disable stage cache
......................................................................
Patch Set 2: Code-Review+2
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Change subject: Kconfig: Allow mainboards to disable stage cache
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Do u see any boot time benefit ?
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Change subject: mb/google/skyrim/var/markarth: Update GPIO settings
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/skyrim/variants/markarth/gpio.c:
https://review.coreboot.org/c/coreboot/+/71635/comment/45683f66_bd44d90b
PS1, Line 4: #include <commonlib/helpers.h>
> No, thanks review.
Done
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Change subject: mb/google/skyrim/var/markarth: Update GPIO settings
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/skyrim/variants/markarth/gpio.c:
https://review.coreboot.org/c/coreboot/+/71635/comment/27c5b880_50b038e4
PS1, Line 4: #include <commonlib/helpers.h>
> do you need this?
No, thanks review.
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Change subject: [WIP] mb/amd/birman: Move EC FW to FMAP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> The EC is put at 0x81000 in UEFI image. If it moves to 15M, is it needed to […]
I assume putting to 0x81000 is a must.
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Change subject: mb/google/nissa: Disable stage cache
......................................................................
mb/google/nissa: Disable stage cache
Although S3 is supported on nissa, only S0ix is used on user devices,
so we don't care about optimising the S3 resume time. Disable the stage
cache to save boot time at the cost on increasing the S3 resume time.
Boot time is reduced by ~6 ms. This is mostly from adding postcar to
the stage cache, which is slow since TSEG is not cached in romstage.
Adding ramstage and FSP-S take negligible time.
The S3 resume time is increased by ~89 ms total from loading and
decompressing ramstage and FSP-S.
Boot time before:
3:after RAM initialization 573,295 (931)
4:end of romstage 583,569 (10,274)
100:start of postcar 587,729 (4,160)
Boot time after:
3:after RAM initialization 571,527 (830)
4:end of romstage 575,712 (4,185)
100:start of postcar 579,866 (4,153)
S3 resume time before:
101:end of postcar 368,904 (0)
10:start of ramstage 369,165 (260)
971:loading FSP-S 385,742 (16,577)
30:device enumeration 407,105 (21,362)
S3 resume time after:
101:end of postcar 363,101 (0)
8:starting to load ramstage 363,101 (0)
15:starting LZMA decompress (ignore for x86) 382,802 (19,701)
16:finished LZMA decompress (ignore for x86) 431,620 (48,817)
9:finished loading ramstage 431,850 (230)
10:start of ramstage 431,927 (76)
971:loading FSP-S 448,357 (16,430)
17:starting LZ4 decompress (ignore for x86) 474,420 (26,062)
18:finished LZ4 decompress (ignore for x86) 474,627 (206)
BUG=b:247940538, b:192032803
TEST=Boot and S3 suspend/resume on craask
Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c
Signed-off-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/71677/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a267946..0b9a089 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -68,6 +68,7 @@
select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select DRIVERS_INTEL_ISH
+ select MAINBOARD_DISABLE_STAGE_CACHE
select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
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Change subject: Kconfig: Allow mainboards to disable stage cache
......................................................................
Kconfig: Allow mainboards to disable stage cache
On recent Intel ChromeOS devices, although S3 is still supported, only
S0ix is used on user devices, so we don't care about optimising S3
resume time. Disabing the stage cache saves boot time at the cost of
increasing the S3 resume time.
BUG=b:247940538, b:192032803
TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE
selected.
Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739
Signed-off-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/Kconfig
1 file changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/71676/1
diff --git a/src/Kconfig b/src/Kconfig
index f16b53c..f68553c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -347,7 +347,7 @@
choice
prompt "Stage Cache for ACPI S3 resume"
- default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
+ default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE
default TSEG_STAGE_CACHE if SMM_TSEG
config NO_STAGE_CACHE
@@ -380,6 +380,13 @@
endchoice
+config MAINBOARD_DISABLE_STAGE_CACHE
+ bool
+ help
+ Selected by mainboards which wish to disable the stage cache.
+ E.g. mainboards which don't use S3 resume in the field may wish to
+ disable it to save boot time at the cost of increasing S3 resume time.
+
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
help
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Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe
......................................................................
Patch Set 11: Code-Review+1
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Change subject: amdfwtool: Allow the amdfw.rom to be split into two parts
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
https://review.coreboot.org/c/coreboot/+/70778
this merged CL has done the job.
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