coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify GPIOs for NVMe
by Ren Kuo (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Martin L Roth. Hello build bot (Jenkins), David Wu, Tarun Tuli, Martin L Roth, Dtrain Hsu, Kangheui Won, Reka Norman, Tyler Wang, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71170 to look at the new patch set (#14). Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe ...................................................................... mb/google/nissa/var/craask: Modify GPIOs for NVMe Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 25 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/71170/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/71170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Gerrit-Change-Number: 71170 Gerrit-PatchSet: 14 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify GPIOs for NVMe
by Ren Kuo (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Martin L Roth. Hello build bot (Jenkins), David Wu, Tarun Tuli, Martin L Roth, Dtrain Hsu, Kangheui Won, Reka Norman, Tyler Wang, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71170 to look at the new patch set (#13). Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe ...................................................................... mb/google/nissa/var/craask: Modify GPIOs for NVMe Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:263920313 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 25 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/71170/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/71170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Gerrit-Change-Number: 71170 Gerrit-PatchSet: 13 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel: Remove dummy _SPECIFIC_OPTIONS
by Elyes Haouas (Code Review) 05 Jan '23

05 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71678 ) Change subject: cpu/intel: Remove dummy _SPECIFIC_OPTIONS ...................................................................... cpu/intel: Remove dummy _SPECIFIC_OPTIONS Change-Id: Iab6deede85c4f6095072a9e0813f70fc8de2c3ef Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_p/Kconfig 11 files changed, 33 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/71678/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index da7d1ab..97ad89b 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -1,11 +1,6 @@ config CPU_INTEL_HASWELL bool - -if CPU_INTEL_HASWELL - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select MMX select SSE2 @@ -20,6 +15,8 @@ select HAVE_ASAN_IN_ROMSTAGE select CPU_INTEL_COMMON_VOLTAGE +if CPU_INTEL_HASWELL + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 5ff809f..24d636e 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_2065X bool - -if CPU_INTEL_MODEL_2065X - -config CPU_SPECIFIC_OPTIONS - def_bool y select HAVE_EXP_X86_64_SUPPORT select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES @@ -17,6 +12,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE +if CPU_INTEL_MODEL_2065X + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c168c9b..c5a7941 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_206AX bool - -if CPU_INTEL_MODEL_206AX - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT @@ -18,6 +13,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE +if CPU_INTEL_MODEL_206AX + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index c30e066..4ba8747 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -2,11 +2,6 @@ config CPU_INTEL_SLOT_1 bool - -if CPU_INTEL_SLOT_1 - -config SLOT_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_65X select CPU_INTEL_MODEL_67X select CPU_INTEL_MODEL_68X @@ -19,6 +14,8 @@ select SETUP_XIP_CACHE select RESERVE_MTRRS_FOR_OS +if CPU_INTEL_SLOT_1 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 2ff419b..f754290 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -1,14 +1,11 @@ config CPU_INTEL_SOCKET_441 bool - -if CPU_INTEL_SOCKET_441 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_106CX select MMX select SETUP_XIP_CACHE +if CPU_INTEL_SOCKET_441 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 464a9b4..b279b4c 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,13 +1,10 @@ config CPU_INTEL_SOCKET_BGA956 bool - -if CPU_INTEL_SOCKET_BGA956 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_1067X select MMX +if CPU_INTEL_SOCKET_BGA956 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index ed661b6..93a55a2 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,16 +1,13 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + select CPU_INTEL_MODEL_106CX + select MMX + select CPU_HAS_L2_ENABLE_MSR help Select this socket on Intel Pineview if CPU_INTEL_SOCKET_FCBGA559 -config SOCKET_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_MODEL_106CX - select MMX - select CPU_HAS_L2_ENABLE_MSR - config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 3c9f262..a47c4d0 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_SOCKET_LGA775 bool - -if CPU_INTEL_SOCKET_LGA775 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -12,6 +7,8 @@ select MMX select SIPI_VECTOR_IN_ROM +if CPU_INTEL_SOCKET_LGA775 + config DCACHE_RAM_SIZE hex default 0x8000 # 32 kB diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 4e74eb4..322d76d 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -1,14 +1,11 @@ config CPU_INTEL_SOCKET_M bool - -if CPU_INTEL_SOCKET_M - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX select MMX +if CPU_INTEL_SOCKET_M + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 12c8e37..0866b92 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_SOCKET_MPGA604 bool - -if CPU_INTEL_SOCKET_MPGA604 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_F2X select MMX select UDELAY_TSC @@ -13,6 +8,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE +if CPU_INTEL_SOCKET_MPGA604 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index e90b42a..552ed70 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -1,14 +1,11 @@ config CPU_INTEL_SOCKET_P bool - -if CPU_INTEL_SOCKET_P - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX select MMX +if CPU_INTEL_SOCKET_P + config DCACHE_RAM_BASE hex default 0xfefc0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/71678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6deede85c4f6095072a9e0813f70fc8de2c3ef Gerrit-Change-Number: 71678 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Add unprovisioned storage fw_config for f...
by Ren Kuo (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, David Wu, Reka Norman, Tyler Wang. Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71681 ) Change subject: mb/google/nissa/var/craask: Add unprovisioned storage fw_config for factory first build ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/71681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I429ef189bf30f581d51058da148eb81f614ed23d Gerrit-Change-Number: 71681 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 06:26:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Add unprovisioned storage fw_config for f...
by Ren Kuo (Code Review) 05 Jan '23

05 Jan '23

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71681 ) Change subject: mb/google/nissa/var/craask: Add unprovisioned storage fw_config for factory first build ...................................................................... mb/google/nissa/var/craask: Add unprovisioned storage fw_config for factory first build In factory build,the storage is a unkonw state in first boot.The storage may be eMMC or NVMe and preflash a dedicated storgae of fw_config in CBI may cause the boot fail if the fw_config's storage not the real storage. Define the STORAGE_UNPROVISIONED in fw_config to support confirgure both NVME and eMMC in depthcharge and avoid close the storage device's GPIOs for first boot in factory. BUG=b:259211172 TEST=Set the storage to unprovisioned and boot up in eMMC and NVMe SKUs. Change-Id: I429ef189bf30f581d51058da148eb81f614ed23d Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/craask/fw_config.c 2 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/71681/1 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 16c7ce0..542fa94 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -7,6 +7,7 @@ option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 + option STORAGE_UNPROVISIONED 3 end end diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index 937e90d..d9b6af8 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -58,6 +58,33 @@ PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), }; +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { @@ -84,9 +111,18 @@ ARRAY_SIZE(stylus_disable_pads)); } - if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { - printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n"); - gpio_padbased_override(padbased_table, nvme_disable_pads, - ARRAY_SIZE(nvme_disable_pads)); + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNPROVISIONED))) { + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { + printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n"); + gpio_padbased_override(padbased_table, nvme_disable_pads, + ARRAY_SIZE(nvme_disable_pads)); + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC SSD GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/71681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I429ef189bf30f581d51058da148eb81f614ed23d Gerrit-Change-Number: 71681 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: spd.h: Move enum ddr2_module_type to ddr2.h
by Reka Norman (Code Review) 05 Jan '23

05 Jan '23

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71546 ) Change subject: spd.h: Move enum ddr2_module_type to ddr2.h ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > Reka, can you review this and next patch? I see you are maintaining SPD Utilities, so you know more […] Sorry I missed this, I've been out for the last couple of weeks. -- To view, visit https://review.coreboot.org/c/coreboot/+/71546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Gerrit-Change-Number: 71546 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 06:03:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Kconfig: Allow mainboards to disable stage cache
by Reka Norman (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kangheui Won, Angel Pons, Arthur Heymans. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71676 ) Change subject: Kconfig: Allow mainboards to disable stage cache ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Do u see any boot time benefit ? Yes, on nissa it saves ~6 ms of boot time. I've added the numbers to the commit message. The following CL also has more details. -- To view, visit https://review.coreboot.org/c/coreboot/+/71676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Gerrit-Change-Number: 71676 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 05 Jan 2023 05:50:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa: Disable stage cache
by Reka Norman (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Reka Norman. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kangheui Won, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71677 to look at the new patch set (#3). Change subject: mb/google/nissa: Disable stage cache ...................................................................... mb/google/nissa: Disable stage cache Although S3 is supported on nissa, only S0ix is used on user devices, so we don't care about optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/71677/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Gerrit-Change-Number: 71677 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Kconfig: Allow mainboards to disable stage cache
by Reka Norman (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Reka Norman, Angel Pons, Arthur Heymans. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kangheui Won, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71676 to look at the new patch set (#3). Change subject: Kconfig: Allow mainboards to disable stage cache ...................................................................... Kconfig: Allow mainboards to disable stage cache On recent Intel ChromeOS devices, although S3 is still supported, only S0ix is used on user devices, so we don't care about optimising S3 resume time. Disabing the stage cache saves boot time at the cost of increasing the S3 resume time. E.g. on nissa this reduces boot time by 6 ms and increases S3 resume time by 89 ms. BUG=b:247940538, b:192032803 TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE selected. Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/Kconfig 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/71676/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Gerrit-Change-Number: 71676 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update GPIO settings
by Eric Lai (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: John Su, Jason Nien, Martin Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71635 ) Change subject: mb/google/skyrim/var/markarth: Update GPIO settings ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Gerrit-Change-Number: 71635 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 05:47:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2023