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Change subject: soc/intel/alderlake: Inform user of memory training
......................................................................
Patch Set 42: Code-Review+1
(2 comments)
Patchset:
PS42:
pending closure on free'ing
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/70300/comment/cf5a4e38_3d00fd7f
PS42, Line 372: "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device.");
wondering if we want to pass const char* instead. However, I recognized this will probably get all reworked with localization in place so probably okay for now.
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Change subject: Documentation/getting_started: Add information about ost2
......................................................................
Patch Set 4:
(4 comments)
File Documentation/getting_started/OST2.md:
https://review.coreboot.org/c/coreboot/+/70853/comment/2b61eaac_ae9e2c59
PS2, Line 7: There are various ways to learn firmware, some are more efficient than others,
> Please add a blank line above, or do not wrap the line.
Done
https://review.coreboot.org/c/coreboot/+/70853/comment/85d5e244_b7291e12
PS2, Line 13: cc BY-SA
> Which version? https://creativecommons.org/licenses/by-sa/1.0/ […]
Done
https://review.coreboot.org/c/coreboot/+/70853/comment/3e2cb20c_89bab216
PS2, Line 27: There are more courses, which can be found [here](https://p.ost2.fyi/courses).
> Please add the missing new line at the end of file.
Done
https://review.coreboot.org/c/coreboot/+/70853/comment/9e76cac8_c8897335
PS2, Line 27: more courses
> Make *more courses* the link. (Maybe add *available*. […]
Done
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Hello build bot (Jenkins), Maciej Pijanowski, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70853
to look at the new patch set (#4).
Change subject: Documentation/getting_started: Add information about ost2
......................................................................
Documentation/getting_started: Add information about ost2
Add links to OpenSecurityTraining2 courses for newcommers
Signed-off-by: Kacper Stojek <kacper.stojek(a)3mdeb.com>
Change-Id: Ifd97996579576b35588fc0db42c16ee20d961760
---
A Documentation/getting_started/OST2.md
M Documentation/getting_started/index.md
2 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/70853/4
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Change subject: soc/intel/common/block/early_graphics: Introduce a 200 ms delay
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/soc/intel/common/block/graphics/early_graphics.c:
https://review.coreboot.org/c/coreboot/+/71656/comment/78f2f795_d2d34e73
PS5, Line 41: * turning off the displays and the PEIM driver initialization is too
nit: reference a specific bug b:264526798
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Change subject: Revert "Revert "mb/google/brya: Add romstage early graphics for brya""
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS23:
> Should we die in coreboot, or let it assert and return from FSP? @Subrata, WDYT?
@Eric,
The implementation has been carried from the previous platform. The reason of making this statement here in coreboot than returning the control to FSP is, we have the board_id check in coreboot itself and however if this doesn't die in coreboot, the control shall return to FSP and die there (invalid condition). This even preserves the fail context wrt coreboot and FSP.
Please do let us know your view here.
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Change subject: soc/intel/common/block: Add Intel VGA early graphics support
......................................................................
Patch Set 27:
(1 comment)
File src/soc/intel/common/block/graphics/early_graphics.c:
https://review.coreboot.org/c/coreboot/+/70299/comment/12836e49_db8ce08b
PS27, Line 6: initialized
> do we have support for global variables?
Only .bss is supported in cache as ram stages, which is zero initialized data. .data (non zero initialized) is not supported. static variables default to 0.
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Change subject: [WIP] mb/amd/birman: Move EC FW to FMAP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I assume putting to 0x81000 is a must.
The EC can be placed at any offset that ends in 00. The first four bytes of the ROM are a signature that tells the EC where to look for its binary.
To move the EC.bin anywhere, the only necessary change is the EC_sig.bin
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