coreboot-gerrit January 2023

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[M] Change in coreboot[master]: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
by Sean Rhodes (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Martin L Roth, Matt DeVillier, John Zhao, Kapil Porwal, Tim Wawrzynczak. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Matt DeVillier, John Zhao, Kapil Porwal, Tim Wawrzynczak, Angel Pons, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64561 to look at the new patch set (#10). Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM ...................................................................... soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 --- M src/device/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/acpi/tcss.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss.asl 7 files changed, 74 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/64561/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/64561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Gerrit-Change-Number: 64561 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Add Kconfig option for Intel Key Locker
by Pratikkumar V Prajapati (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Felix Singer, Paul Menzel, Sridhar Siricilla. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71118 ) Change subject: soc/intel/common: Add Kconfig option for Intel Key Locker ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: I have removed the link to the spec and kept document # only. -- To view, visit https://review.coreboot.org/c/coreboot/+/71118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Gerrit-Change-Number: 71118 Gerrit-PatchSet: 14 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:33:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Untie PRMRR from SGX
by Pratikkumar V Prajapati (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla. Hello Will Kim, build bot (Jenkins), Tarun Tuli, Subrata Banik, Wonkyu Kim, Kapil Porwal, Sridhar Siricilla, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70819 to look at the new patch set (#22). Change subject: soc/intel/common: Untie PRMRR from SGX ...................................................................... soc/intel/common: Untie PRMRR from SGX PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/sgx/Kconfig 3 files changed, 85 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/70819/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/70819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Gerrit-Change-Number: 70819 Gerrit-PatchSet: 22 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Will Kim <norwayforest92(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Add Kconfig option for Intel Key Locker
by Pratikkumar V Prajapati (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Felix Singer, Paul Menzel, Sridhar Siricilla. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71118 to look at the new patch set (#14). Change subject: soc/intel/common: Add Kconfig option for Intel Key Locker ...................................................................... soc/intel/common: Add Kconfig option for Intel Key Locker Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The specification of Key Locker can be found via document #343965 on Intel's site. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/71118/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/71118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Gerrit-Change-Number: 71118 Gerrit-PatchSet: 14 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/alderlake: Inform user of memory training
by Jérémy Compostella (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Bora Guvendik, Anil Kumar K, Hannah Williams, Cliff Huang, Paul Menzel, Angel Pons, Arthur Heymans, Andrey Petrov, Zhixing Ma, Tarun Tuli, Nico Huber, Michał Żygowski, Subrata Banik, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70300 ) Change subject: soc/intel/alderlake: Inform user of memory training ...................................................................... Patch Set 42: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/70300/comment/b4e14a7f_ef00a1ef PS42, Line 372: "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device."); > wondering if we want to pass const char* instead. […] I am confused this is already a `const char *`. Do you mean an NULL terminated array of `const char *`. Is there a new function taking that as an input ? -- To view, visit https://review.coreboot.org/c/coreboot/+/70300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Gerrit-Change-Number: 70300 Gerrit-PatchSet: 42 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:26:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage
by Arthur Heymans (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71675 ) Change subject: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Gerrit-Change-Number: 71675 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:18:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage
by Arthur Heymans (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71675 ) Change subject: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71675/comment/da134ed0_db27f44a PS1, Line 20: Right now we have 2MiB empty space in Skyrim's RO before this change, : and roughly 550KiB empty space in RW, so there aren't currently any : size worries. Maybe it's worth mentioning that this just changes the default so that it's still possible to maximally use the flash for big LinuxBoot payloads ;-) Patchset: PS1: Nice! I vaguely remember having similar speedups for ramstage decompressing when going from LZMA to ZSTD on a picasso board, that one does not use DMA however. -- To view, visit https://review.coreboot.org/c/coreboot/+/71675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Gerrit-Change-Number: 71675 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:18:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Kconfig: Add option to compress ramstage with LZ4
by Arthur Heymans (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Martin L Roth, Julius Werner, Martin Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71673 ) Change subject: Kconfig: Add option to compress ramstage with LZ4 ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: Interesting that decompression is actually the bottleneck here. File src/Kconfig: https://review.coreboot.org/c/coreboot/+/71673/comment/19063588_1f2e8106 PS1, Line 173: config MB_COMPRESS_RAMSTAGE_LZ4 > I wonder if this should be a variable affecting both payload compression and ramstage compression, because if LZ4 is better for one of them it would likely be better for the other as well? It could be a sort of generic PREFER_LZ4 option that affects all compression choices. It's quite complicated on x86 as caching has a big impact on performance, which to complicate things is platform dependent. How caching is set changes a lot during boot / at the moment of decompression. For instance when loading ramstage the ROM is often cached, but sometimes not when loading the payload. This also depends on the algo used. For instance with lzma it looks like caching the source does not have a big impact but with zstd the performance changes a lot. https://review.coreboot.org/c/coreboot/+/71673/comment/9de47621_92ed3df1 PS1, Line 192: Compress ramstage with LZ4 for faster decompression > It would be good to explain the trade-offs involved in this decision (e.g. flash reading speed vs CPU speed and flash space) in more detail in one of these help strings. That's a pretty complicated to get right because it depends on a lot of things. It's a good idea to document a few things that could impact the decision, but in the end it's a trial and error process since most of the hardware is a black box to us (e.g. caching behavior). -- To view, visit https://review.coreboot.org/c/coreboot/+/71673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Gerrit-Change-Number: 71673 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:11:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
by Nick Vaccaro (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Ren Kuo, Nick Vaccaro. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71628 ) Change subject: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/kano/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71628/comment/d190cbe0_feb22040 PS1, Line 20: option UFC_MIPI_OVTI2740 0 > You can refer to CB:70881. […] How does the code know whether or not to use SSFC given both kano and zydron will use a kano firmare image? My appologies for not knowing more about how SSFC works, am asking around now to try to get more information on it. -- To view, visit https://review.coreboot.org/c/coreboot/+/71628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46fac6c820d6006956680a07198db82225630905 Gerrit-Change-Number: 71628 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:04:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add Kconfig option for Intel Key Locker
by Pratikkumar V Prajapati (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Felix Singer, Paul Menzel, Sridhar Siricilla. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71118 ) Change subject: soc/intel/common: Add Kconfig option for Intel Key Locker ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/71118/comment/8dd2b913_fe6b7deb PS13, Line 173: ification.html > can you indent the line? as Paul Menzel mentioned "Please put the URL in one line.". I have kept the URL in one line. -- To view, visit https://review.coreboot.org/c/coreboot/+/71118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Gerrit-Change-Number: 71118 Gerrit-PatchSet: 13 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 16:43:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2023