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Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71673 )
Change subject: Kconfig: Add option to compress ramstage with LZ4
......................................................................
Patch Set 2:
(5 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/71673/comment/3db89bdf_60d840f1
PS1, Line 173: config MB_COMPRESS_RAMSTAGE_LZ4
> > I wonder if this should be a variable affecting both payload compression and ramstage compression, […]
Changing FSP-M to LZ4 instead of LZMA slowed things down significantly, so I think it's worth having the options for various different areas.
I do agree that the selection process is somewhat kludgy right now, and maybe we should look at updating the entire compression configuration, but I'd rather do that separately than this patch.
Also, because ChromeOS adds the payload separately from the coreboot build, we need to modify a USE flag to change the payload compression.
https://review.coreboot.org/c/coreboot/+/71673/comment/4127c06f_1b25039e
PS1, Line 180: depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE
> I forget, what actually happens when the depends on in a choice is not satisfied? Does that mean bot […]
The option is set to false and hidden. This depends on was previously just lower in the Kconfig, so nothing is actually changed because of this.
https://review.coreboot.org/c/coreboot/+/71673/comment/50145b44_36a4a151
PS1, Line 181: default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4
> Don't you still need a `default COMPRESS_RAMSTAGE_LZMA` after this as well?
No, the first option will be the default if there's no other default specified. If you'd like it specified, I can add the default, but it's not actually needed.
https://review.coreboot.org/c/coreboot/+/71673/comment/87571d69_447ecde5
PS1, Line 185: # Default value set at the end of the file
> This comment no longer seems accurate
Thanks. Updated.
https://review.coreboot.org/c/coreboot/+/71673/comment/f8aa7a86_c841030d
PS1, Line 192: Compress ramstage with LZ4 for faster decompression
> > It would be good to explain the trade-offs involved in this decision (e.g. […]
Yeah, this was kind of a throw-away help string on my part. I don't think I can really offer general advice though, because as arthur says, it's complicated and the speed will depend on the platform.
I think we can definitely say that lZ4 offers faster decompression, but oviously that doesn't always mean a lower boot time.
Maybe
Compress ramstage with LZ4.
This offers less compression but better decompression speed - you will need to test the
compression options to determine what's best for your platform.
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Change subject: soc/intel/common: Check PRMRR dependent features
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71569/comment/5fa2d0b6_9692f32e
PS10, Line 7: dd helper functions for SGX, Key Locker, and PRM
> The primary purpose of this CL seems to be setting PRMRR to 0 if all PRM features are disabled.
updated commit msg
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/71569/comment/f1f262eb_098bb4af
PS10, Line 436: configured
> Sounds misleading to me. 'configured' vs 'CONFIG enabled'.
Does not seem misleading but do you have any better recommendation? I can change the function names.
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Hello build bot (Jenkins), Subrata Banik, Sridhar Siricilla,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71569
to look at the new patch set (#11).
Change subject: soc/intel/common: Check PRMRR dependent features
......................................................................
soc/intel/common: Check PRMRR dependent features
Add below mentioned functions:
is_sgx_configured_and_supported():
Checks if SGX is configured and supported
is_keylocker_configured_and_supported():
Checks if Key Locker is configured and supported
check_prm_features_enabled():
Checks if any of the features that need PRM are configured
and supported. As of now SGX and Key Locker are the only
features that need PRM.
Also, call check_prm_features_enabled() from get_valid_prmrr_size()
to make sure PRM dependent features are enabled and configured before
returning PRMRR size.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9
---
M src/soc/intel/common/block/cpu/cpulib.c
1 file changed, 71 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/71569/11
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Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70300 )
Change subject: soc/intel/alderlake: Inform user of memory training
......................................................................
Patch Set 43:
(2 comments)
Patchset:
PS42:
> pending closure on free'ing
Done.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/70300/comment/03a0fb75_d6305484
PS42, Line 372: "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device.");
> to clarify, passed to the inform_user_of_memory_training function. […]
okay.
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Change subject: soc/intel/alderlake: Add romstage early graphics support
......................................................................
Patch Set 47:
(2 comments)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/70303/comment/265398a3_59962bac
PS42, Line 211: 0xfa000000
> > I understand but the change you have recommended, libgfinit does not run anymore in both romstage […]
I am sorry, were you trying to respond ?
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/70303/comment/ad894727_370ca2fb
PS46, Line 427: m_cfg->GttMmAdr = CONFIG_GFX_GMA_DEFAULT_MMIO;
> for user without LIBGFXINIT config being selected this value could be 0. […]
I guarded it with `HWBASE_STATIC_MMIO` as `CONFIG` cannot work with non-boolean `CONFIG_GFX_GMA_DEFAULT_MMIO`.
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Hello build bot (Jenkins), Tarun Tuli,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/intel/common/block/early_graphics: Introduce a 200 ms delay
......................................................................
soc/intel/common/block/early_graphics: Introduce a 200 ms delay
It has been reported that the PEIM graphics driver may temporarily
fail communication with the display if the time between libgfxinit
turning off the displays and the PEIM driver initialization is too
short. 200 ms has been identified as a safe delay.
This is a temporary workaround and an investigation is in progress to
come up with a better and long term solution.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is systematically seen
Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/graphics/early_graphics.c
1 file changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/71656/6
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