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Change subject: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
......................................................................
Patch Set 1: Code-Review+2
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Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71707 )
Change subject: mb/google/nissa: Enable eNEM
......................................................................
mb/google/nissa: Enable eNEM
Enable eNEM for all nissa variants. This is mostly done to be consistent
with other recent Intel platforms. It's not strictly necessary since on
nissa the LLC size is larger than the total code + data size used in
CAR. There is no change in boot time.
BUG=None
TEST=Boot to OS on craask
Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd
Signed-off-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/71707/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9f0c223..d8b52c9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -299,7 +299,7 @@
choice
prompt "Cache as RAM (CAR) setup configuration to use"
- default USE_ADL_NEM if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU || BOARD_GOOGLE_YAVIKS || BOARD_GOOGLE_ZYDRON
+ default USE_ADL_NEM if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_ZYDRON
default USE_ADL_ENEM
config USE_ADL_ENEM
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Change subject: mb/starlabs: Remove the bios_version function
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/nissa/var/xivu: Update DPTF parameters
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/xivu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71658/comment/2a3cbff1_e4a139d7
PS1, Line 158: CPU
Should this be CHARGER?
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71187
to look at the new patch set (#2).
Change subject: mb/google/dedede: Implement touchscreen power sequencing
......................................................................
mb/google/dedede: Implement touchscreen power sequencing
For touchscreens on dedede variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).
Since the fast majority of dedede variants have a touchscreen option, and
those that do use the same GPIOs for enable/reset, set the GPIOs for
touchscreen operation in the baseboard and then override for the few (3)
variants that do not have a touchscreen.
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/dedede/variants/baseboard/gpio.c
M src/mainboard/google/dedede/variants/beadrix/gpio.c
M src/mainboard/google/dedede/variants/cappy2/gpio.c
M src/mainboard/google/dedede/variants/sasuke/gpio.c
4 files changed, 85 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/71187/2
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Change subject: mb/google/nissa: Disable stage cache
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71677/comment/d5656f9f_4eea7953
PS3, Line 10: don't care about
> nit: can ignore
Done
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kangheui Won, Sridhar Siricilla, Eric Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa: Disable stage cache
......................................................................
mb/google/nissa: Disable stage cache
Although S3 is supported on nissa, only S0ix is used on user devices,
so we can ignore optimising the S3 resume time. Disable the stage
cache to save boot time at the cost on increasing the S3 resume time.
Boot time is reduced by ~6 ms. This is mostly from adding postcar to
the stage cache, which is slow since TSEG is not cached in romstage.
Adding ramstage and FSP-S take negligible time.
The S3 resume time is increased by ~89 ms total from loading and
decompressing ramstage and FSP-S.
Boot time before:
3:after RAM initialization 573,295 (931)
4:end of romstage 583,569 (10,274)
100:start of postcar 587,729 (4,160)
Boot time after:
3:after RAM initialization 571,527 (830)
4:end of romstage 575,712 (4,185)
100:start of postcar 579,866 (4,153)
S3 resume time before:
101:end of postcar 368,904 (0)
10:start of ramstage 369,165 (260)
971:loading FSP-S 385,742 (16,577)
30:device enumeration 407,105 (21,362)
S3 resume time after:
101:end of postcar 363,101 (0)
8:starting to load ramstage 363,101 (0)
15:starting LZMA decompress (ignore for x86) 382,802 (19,701)
16:finished LZMA decompress (ignore for x86) 431,620 (48,817)
9:finished loading ramstage 431,850 (230)
10:start of ramstage 431,927 (76)
971:loading FSP-S 448,357 (16,430)
17:starting LZ4 decompress (ignore for x86) 474,420 (26,062)
18:finished LZ4 decompress (ignore for x86) 474,627 (206)
BUG=b:247940538, b:192032803
TEST=Boot and S3 suspend/resume on craask
Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c
Signed-off-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/71677/4
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71673 )
Change subject: Kconfig: Add option to compress ramstage with LZ4
......................................................................
Patch Set 2:
(4 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/71673/comment/16a06b29_c44283dc
PS1, Line 173: config MB_COMPRESS_RAMSTAGE_LZ4
> Changing FSP-M to LZ4 instead of LZMA slowed things down significantly, so I think it's worth having […]
Ack
https://review.coreboot.org/c/coreboot/+/71673/comment/b7310957_a084df33
PS1, Line 180: depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE
> The option is set to false and hidden. […]
Ack
https://review.coreboot.org/c/coreboot/+/71673/comment/72184e00_d0fbfec3
PS1, Line 181: default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4
> No, the first option will be the default if there's no other default specified. […]
Yes, please do, I think we're doing that on all choice options. That it automatically defaults to the first is news to me, that seems like a very obscure thing to rely upon.
https://review.coreboot.org/c/coreboot/+/71673/comment/16832ae0_6f92cd6f
PS1, Line 192: Compress ramstage with LZ4 for faster decompression
> Yeah, this was kind of a throw-away help string on my part. […]
Sure, I'm not saying that you can explain every possible situation here, just give people an idea what the relevant factors are (as far as we know them). It would also be good to add that it can be complicated and should always be tested in practice.
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Change subject: mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71675/comment/c34f097b_57457b54
PS1, Line 20: Right now we have 2MiB empty space in Skyrim's RO before this change,
: and roughly 550KiB empty space in RW, so there aren't currently any
: size worries.
> Maybe it's worth mentioning that this just changes the default so that it's still possible to maxima […]
Unfortunately, these are different regions than what's used for the payloads.
Patchset:
PS1:
> Nice! I vaguely remember having similar speedups for ramstage decompressing when going from LZMA to […]
I bet we'd get big improvements again with switching to ZSTD. Looking forward to that being an option.
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