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Change subject: soc/intel/alderlake: Add romstage early graphics support
......................................................................
soc/intel/alderlake: Add romstage early graphics support
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Verify that VGA text mode is functional in romstage
Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/Makefile.inc
M src/soc/intel/alderlake/romstage/fsp_params.c
A src/soc/intel/alderlake/romstage/graphics.c
5 files changed, 115 insertions(+), 0 deletions(-)
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Change subject: soc/intel/common: Add common function to disable LT memory lock
......................................................................
soc/intel/common: Add common function to disable LT memory lock
Add a common function to unlock memory by setting MSR 0x2e6 to 0. If
internal chipset conditions are met, it unlocks access to the DRAM.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=romstage early graphics is operational
Change-Id: Ic666919ed51f683c9a1ef0b7ba061cd2949faf1e
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
3 files changed, 28 insertions(+), 0 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block: Add Intel VGA early graphics support
......................................................................
soc/intel/common/block: Add Intel VGA early graphics support
This patch introduces an early graphics driver which can be used in
romstage in cache-as-ram mode. The implementation relies on
`libgfxinit' and provide VGA text mode support.
SoCs wanting to take advantage of this driver must implement the
following functions:
- `void early_graphics_soc_device_init(void)' to set the
graphic device MMIO to the `CONFIG_GFX_GMA_DEFAULT_MMIO'
value (typically PCI graphic device Base Address Register 0).
- `void early_graphics_soc_panel_init(void)' to set the panel power
sequence timing parameters.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Graphics bring up observed on skolas with extra patches
Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/gma/gma-gfx_init.ads
M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb
M src/drivers/intel/gma/libgfxinit.h
M src/drivers/intel/gma/text_fb/gma-gfx_init.adb
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/Makefile.inc
A src/soc/intel/common/block/graphics/early_graphics.c
A src/soc/intel/common/block/include/intelblocks/early_graphics.h
8 files changed, 131 insertions(+), 0 deletions(-)
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Change subject: soc/amd/morgana: update max number of cpus to 16 for morgana
......................................................................
soc/amd/morgana: update max number of cpus to 16 for morgana
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
---
M src/soc/amd/morgana/Kconfig
M src/soc/amd/morgana/cpu.c
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Change subject: soc/amd/morgana: update max number of cpus to 16 for morgana
......................................................................
soc/amd/morgana: update max number of cpus to 16 for morgana
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
---
M src/soc/amd/morgana/Kconfig
M src/soc/amd/morgana/cpu.c
2 files changed, 11 insertions(+), 2 deletions(-)
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ritul guru has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71688 )
Change subject: soc/amd/morgana: update max number of cpus to 16 for margana
......................................................................
soc/amd/morgana: update max number of cpus to 16 for margana
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
---
M src/soc/amd/morgana/Kconfig
M src/soc/amd/morgana/cpu.c
2 files changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/71688/1
diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig
index 7765f92..ce57540 100644
--- a/src/soc/amd/morgana/Kconfig
+++ b/src/soc/amd/morgana/Kconfig
@@ -238,7 +238,6 @@
config MAX_CPUS
int
- default 8 if SOC_AMD_MORGANA
default 16
help
Maximum number of threads the platform can have.
diff --git a/src/soc/amd/morgana/cpu.c b/src/soc/amd/morgana/cpu.c
index fe5a1b8..68c3a34 100644
--- a/src/soc/amd/morgana/cpu.c
+++ b/src/soc/amd/morgana/cpu.c
@@ -16,7 +16,7 @@
#include <soc/cpu.h>
#include <soc/iomap.h>
-_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
+_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization */
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Change subject: mb/amd/mayan: update EC FW offset in spirom
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/amd/mayan/Kconfig:
https://review.coreboot.org/c/coreboot/+/70540/comment/196039fe_ad74867f
PS1, Line 61: default 0x81000
> this is mainboard specific bios rom offset which will be fixed, do we see a need of user configurabl […]
Ack
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71687 )
Change subject: soc/intel: Add Kconfigs to define scaling factor for cores
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/71687/comment/3641f0ec_64c3a740
PS1, Line 78: soc_get_scaling_factor
> Do we even need this function now?
Agreed. Maybe add some _Static_assert() on the CONFIG_SOC_INTEL_PERF_CORE_SCAL_FACTOR as a way to make sure that those are properly defined and configured (non zero).
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