coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

[M] Change in coreboot[master]: soc/intel/: Rename small and big cores references
by Arthur Heymans (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71639 ) Change subject: soc/intel/: Rename small and big cores references ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f Gerrit-Change-Number: 71639 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 18:21:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common: Fix cpu index calculation
by Arthur Heymans (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh, Sukumar Ghorai, Raj Astekar. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70751 ) Change subject: soc/intel/common: Fix cpu index calculation ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Gerrit-Change-Number: 70751 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 18:20:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM
by Kapil Porwal (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Pratikkumar V Prajapati. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71569 ) Change subject: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71569/comment/72e2a146_d19602f3 PS10, Line 7: dd helper functions for SGX, Key Locker, and PRM The primary purpose of this CL seems to be setting PRMRR to 0 if all PRM features are disabled. File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/71569/comment/4cc5bcaf_15359236 PS10, Line 436: configured Sounds misleading to me. 'configured' vs 'CONFIG enabled'. -- To view, visit https://review.coreboot.org/c/coreboot/+/71569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Gerrit-Change-Number: 71569 Gerrit-PatchSet: 10 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 18:12:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/alderlake: Inform user of memory training
by Tarun Tuli (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Bora Guvendik, Anil Kumar K, Hannah Williams, Cliff Huang, Jérémy Compostella, Paul Menzel, Angel Pons, Arthur Heymans, Andrey Petrov, Zhixing Ma, Nico Huber, Michał Żygowski, Subrata Banik, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70300 ) Change subject: soc/intel/alderlake: Inform user of memory training ...................................................................... Patch Set 42: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/70300/comment/ca5711dd_121d27c3 PS42, Line 372: "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device."); > I am confused this is already a `const char *`. […] to clarify, passed to the inform_user_of_memory_training function. But I suggest we wait on this until we see how localization is going to work... -- To view, visit https://review.coreboot.org/c/coreboot/+/70300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Gerrit-Change-Number: 70300 Gerrit-PatchSet: 42 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 18:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update GPIO settings
by Martin L Roth (Code Review) 05 Jan '23

05 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71635 ) Change subject: mb/google/skyrim/var/markarth: Update GPIO settings ...................................................................... mb/google/skyrim/var/markarth: Update GPIO settings Configure GPIOs based on b/263534907#comment4 from EE. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/markarth/Makefile.inc A src/mainboard/google/skyrim/variants/markarth/gpio.c 2 files changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc index 88e75bd..83f7700 100644 --- a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./memory +ramstage-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/markarth/gpio.c b/src/mainboard/google/skyrim/variants/markarth/gpio.c new file mode 100644 index 0000000..9753179 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/gpio.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +/* GPIO configuration in ramstage */ +static const struct soc_amd_gpio override_gpio_table[] = { + + /* SOC_PEN_DETECT_ODL => Unused */ + PAD_NC(GPIO_3), + /* EN_PWR_FP => Unused */ + PAD_NC(GPIO_4), + /* EN_PWR_WWAN_X => Unused */ + PAD_NC(GPIO_8), + /* SOC_FP_INT_L => Unused */ + PAD_NC(GPIO_24), + /* SD_AUX_RST_SOC_L => Unused */ + PAD_NC(GPIO_27), + /* WWAN_RST_L => Unused */ + PAD_NC(GPIO_42), +}; + +void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(override_gpio_table); + *gpio = override_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Gerrit-Change-Number: 71635 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: Update vboot submodule to upstream main
by Martin L Roth (Code Review) 05 Jan '23

05 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71582 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id 196b0843e9 : to a09b792e6a : Makefile: Remove old include directories This brings in 9 new commits. Fix: cc1: error: firmware/lib/cryptolib/include: No such file or directory [-Werror=missing-include-dirs] cc1: error: firmware/lib20/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71582 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/vboot 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index 196b084..a09b792 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 196b0843e90cfa791123d1fff88eca06721dc64a +Subproject commit a09b792e6a159d7d21b8e64f07a056ba08f8014d -- To view, visit https://review.coreboot.org/c/coreboot/+/71582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4 Gerrit-Change-Number: 71582 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun
by Martin L Roth (Code Review) 05 Jan '23

05 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71647 ) Change subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun ...................................................................... mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647 Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Jason Glenesk: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 1d50bd5..b4e7c46 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -99,6 +99,9 @@ register "stt_skin_temp_apu_F" = "0x3200" device domain 0 on + + register "dxio_tx_vboost_enable" = "1" + device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device -- To view, visit https://review.coreboot.org/c/coreboot/+/71647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Gerrit-Change-Number: 71647 Gerrit-PatchSet: 7 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/brya/var/marasov: Disable FPMCU interface
by Martin L Roth (Code Review) 05 Jan '23

05 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71650 ) Change subject: mb/google/brya/var/marasov: Disable FPMCU interface ...................................................................... mb/google/brya/var/marasov: Disable FPMCU interface Set fingerprint control GPIO to NC by HW design. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71650 Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/marasov/gpio.c 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/marasov/gpio.c b/src/mainboard/google/brya/variants/marasov/gpio.c index 032922a..745861f 100644 --- a/src/mainboard/google/brya/variants/marasov/gpio.c +++ b/src/mainboard/google/brya/variants/marasov/gpio.c @@ -100,6 +100,16 @@ PAD_NC(GPP_E21, NONE), /* F6 : WWAN_WLAN_COEX3 ==> NC */ PAD_NC(GPP_F6, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F19 : GPP_F19(TP93) ==> NC */ PAD_NC(GPP_F19, NONE), /* F20 : UCAM_RST_L ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Gerrit-Change-Number: 71650 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/system76/tgl-u: Add FSP-S configs per variant
by Martin L Roth (Code Review) 05 Jan '23

05 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71558 ) Change subject: mb/system76/tgl-u: Add FSP-S configs per variant ...................................................................... mb/system76/tgl-u: Add FSP-S configs per variant Configure CPU PCIe RP and IOM per variant. Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/tgl-u/Makefile.inc M src/mainboard/system76/tgl-u/ramstage.c A src/mainboard/system76/tgl-u/variants/darp7/ramstage.c A src/mainboard/system76/tgl-u/variants/galp5/ramstage.c A src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c 5 files changed, 61 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/tgl-u/Makefile.inc b/src/mainboard/system76/tgl-u/Makefile.inc index 845c39a..ca14835 100644 --- a/src/mainboard/system76/tgl-u/Makefile.inc +++ b/src/mainboard/system76/tgl-u/Makefile.inc @@ -12,5 +12,6 @@ ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c index d4cb898..a01391a 100644 --- a/src/mainboard/system76/tgl-u/ramstage.c +++ b/src/mainboard/system76/tgl-u/ramstage.c @@ -9,12 +9,6 @@ return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; } -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - // Disable AER to fix suspend failing with some SSDs. - params->CpuPcieRpAdvancedErrorReporting[0] = 0; -} - static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c new file mode 100644 index 0000000..a60587d --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c new file mode 100644 index 0000000..a60587d --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c new file mode 100644 index 0000000..2064836 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Disable AER to fix suspend failing with some SSDs. + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[2] = 1; // J_TYPEC1 +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9 Gerrit-Change-Number: 71558 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
by Sean Rhodes (Code Review) 05 Jan '23

05 Jan '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Matt DeVillier, John Zhao, Kapil Porwal, Tim Wawrzynczak. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64561 ) Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/alderlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/64561/comment/f65cd208_e83f801a PS7, Line 164: #if CONFIG(CHROMEOS) > > Like PS8? […] Done File src/soc/intel/meteorlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/64561/comment/d8b3a6ee_50d0c063 PS9, Line 158: #if CONFIG(SOFTWARE_CONNECTION_MANAGER) > > unlike ADL/TGL, SCM is always disabled for MTL. Is this expected? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Gerrit-Change-Number: 64561 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 05 Jan 2023 17:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2023