coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
by Eric Lai (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Reka Norman. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71690 ) Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This CL is along with https://chrome-internal-review.googlesource.com/c/chromeos/project/nissa/cr… -- To view, visit https://review.coreboot.org/c/coreboot/+/71690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Gerrit-Change-Number: 71690 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Jan 2023 01:33:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
by Eric Lai (Code Review) 06 Jan '23

06 Jan '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71690 ) Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config ...................................................................... mb/google/nissa/var/craask: remove SAR UNUSED fw_config This bit is dropped in factory. All skus can use table ID_0. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/71690/1 diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 1a733fb..65b963a 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -22,7 +22,6 @@ end field WIFI_SAR_ID 13 15 option ID_0 0 - option UNUSED 7 end field CODEC 32 33 option CODEC_ALC5682I_VS 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/71690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Gerrit-Change-Number: 71690 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/alderlake: Inform user of memory training
by Jérémy Compostella (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Bora Guvendik, Anil Kumar K, Hannah Williams, Cliff Huang, Paul Menzel, Angel Pons, Arthur Heymans, Andrey Petrov, Zhixing Ma, Tarun Tuli, Nico Huber, Michał Żygowski, Subrata Banik, Nick Vaccaro. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Cliff Huang, Paul Menzel, Angel Pons, Arthur Heymans, Andrey Petrov, Zhixing Ma, Tarun Tuli, Nico Huber, Michał Żygowski, Subrata Banik, Nick Vaccaro, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70300 to look at the new patch set (#44). Change subject: soc/intel/alderlake: Inform user of memory training ...................................................................... soc/intel/alderlake: Inform user of memory training If memory training is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On screen text message during MRC training observed on skolas Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/70300/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/70300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Gerrit-Change-Number: 70300 Gerrit-PatchSet: 44 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: use i2c1 for TPM
by Eric Lai (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Jamie Chen, Tarun Tuli, Dtrain Hsu, Ian Feng. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71703 ) Change subject: mb/google/brya/var/omnigul: use i2c1 for TPM ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Gerrit-Change-Number: 71703 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 00:36:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/google: Add and use POST_CODE_CLEAR definition
by Eric Lai (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71592 ) Change subject: vc/google: Add and use POST_CODE_CLEAR definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Gerrit-Change-Number: 71592 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 Jan 2023 00:32:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/google: Add and use POST_CODE_CLEAR definition
by Jon Murphy (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Martin L Roth, Felix Held. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71592 ) Change subject: vc/google: Add and use POST_CODE_CLEAR definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Gerrit-Change-Number: 71592 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 Jan 2023 00:31:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Eric Lai (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: (1 comment) Patchset: PS23: > @Eric, […] IIRC, last time I learned we should try boot as far as possible and let it stuck the right place if this will die later after fsp-m. we don't have to block here. -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 06 Jan 2023 00:22:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Kconfig: Add option to compress ramstage with LZ4
by Martin L Roth (Code Review) 06 Jan '23

06 Jan '23

Attention is currently required from: Julius Werner, Arthur Heymans, Martin Roth, Fred Reitberger. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71673 ) Change subject: Kconfig: Add option to compress ramstage with LZ4 ...................................................................... Patch Set 3: (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/71673/comment/9846ad4b_792aa22e PS1, Line 181: default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4 > Yes, please do, I think we're doing that on all choice options. […] Added. https://review.coreboot.org/c/coreboot/+/71673/comment/c50e86b4_e1cdfc27 PS1, Line 192: Compress ramstage with LZ4 for faster decompression > Sure, I'm not saying that you can explain every possible situation here, just give people an idea wh […] Sounds good - Updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/71673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Gerrit-Change-Number: 71673 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Jan 2023 00:12:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP, POC]: Save postcode data to CBFS
by build bot (Jenkins) (Code Review) 05 Jan '23

05 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71708 ) Change subject: [WIP, POC]: Save postcode data to CBFS ...................................................................... Patch Set 1: (3 comments) File src/include/console/console.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167764): https://review.coreboot.org/c/coreboot/+/71708/comment/e63621c0_1bef94e1 PS1, Line 24: #define POST_CODE_INIT_ATTR __attribute__((used, section(".post_code"))) Prefer __used over __attribute__((used)) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167764): https://review.coreboot.org/c/coreboot/+/71708/comment/db68a757_8e96c1d4 PS1, Line 24: #define POST_CODE_INIT_ATTR __attribute__((used, section(".post_code"))) Prefer __section(".post_code") over __attribute__((section(".post_code"))) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167764): https://review.coreboot.org/c/coreboot/+/71708/comment/058a004c_cafdd938 PS1, Line 35: static struct post_code_entry POST_CODE_INIT_ATTR POSTCODE_## VALUE = \ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/71708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b6e79a29235baaff7b744ab1c97ddaf64af391 Gerrit-Change-Number: 71708 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jan 2023 23:43:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP, POC]: Save postcode data to CBFS
by Martin L Roth (Code Review) 05 Jan '23

05 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71708 ) Change subject: [WIP, POC]: Save postcode data to CBFS ...................................................................... [WIP, POC]: Save postcode data to CBFS This is currently just in the proof of concept phase. It uses a macro to save the postcodes to a .post_code section in the object files. That section can later be retrieved to build up a table of all of the post codes used in a ROM. This table can be used by a future tool to parse postcode lists or even to just make a postcode table specific to a particular board/image. This means that postcodes must actually be defined, and can't be used as bare values, which is why hardwaremain.c needed to be updated. I don't see that as a particularly big issue, as we want them defined anyway. To allow for debug and test to use arbitrary values and dump other data out of the postcode port, a separate macro will need to be developed. To extract the data from the object files, use this command: for file in $(find build -name 'build/*.o'); do \ objcopy -j .post_code -O binary "${file}" "${file}.pc"; \ cat "${file}.pc" >> postcodes.bin ; \ done TODO: Add the object parsing to the Makefile, write some scripts to use the output. Intentionally not signed off so that the builder won't build this until it's closer to being ready. Change-Id: Ia4b6e79a29235baaff7b744ab1c97ddaf64af391 --- M src/commonlib/include/commonlib/console/post_codes.h M src/console/Kconfig M src/console/post.c M src/include/console/console.h M src/lib/hardwaremain.c 5 files changed, 384 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/71708/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..8538085 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -464,4 +464,261 @@ */ #define POST_DIE 0xff +#define POST_STRING_0x00 "" +#define POST_STRING_0x01 "" +#define POST_STRING_0x02 "" +#define POST_STRING_0x03 "" +#define POST_STRING_0x04 "" +#define POST_STRING_0x05 "" +#define POST_STRING_0x06 "" +#define POST_STRING_0x07 "" +#define POST_STRING_0x08 "" +#define POST_STRING_0x09 "" +#define POST_STRING_0x0a "" +#define POST_STRING_0x0b "" +#define POST_STRING_0x0c "" +#define POST_STRING_0x0d "" +#define POST_STRING_0x0e "" +#define POST_STRING_0x0f "" +#define POST_STRING_0x10 "" +#define POST_STRING_0x11 "" +#define POST_STRING_0x12 "" +#define POST_STRING_0x13 "" +#define POST_STRING_0x14 "" +#define POST_STRING_0x15 "" +#define POST_STRING_0x16 "" +#define POST_STRING_0x17 "" +#define POST_STRING_0x18 "" +#define POST_STRING_0x19 "" +#define POST_STRING_0x1a "" +#define POST_STRING_0x1b "" +#define POST_STRING_0x1c "" +#define POST_STRING_0x1d "" +#define POST_STRING_0x1e "" +#define POST_STRING_0x1f "" +#define POST_STRING_0x20 "" +#define POST_STRING_0x21 "" +#define POST_STRING_0x22 "" +#define POST_STRING_0x23 "" +#define POST_STRING_0x24 "" +#define POST_STRING_0x25 "" +#define POST_STRING_0x26 "" +#define POST_STRING_0x27 "" +#define POST_STRING_0x28 "" +#define POST_STRING_0x29 "" +#define POST_STRING_0x2a "" +#define POST_STRING_0x2b "" +#define POST_STRING_0x2c "" +#define POST_STRING_0x2d "" +#define POST_STRING_0x2e "" +#define POST_STRING_0x2f "" +#define POST_STRING_0x30 "" +#define POST_STRING_0x31 "" +#define POST_STRING_0x32 "" +#define POST_STRING_0x33 "" +#define POST_STRING_0x34 "" +#define POST_STRING_0x35 "" +#define POST_STRING_0x36 "" +#define POST_STRING_0x37 "" +#define POST_STRING_0x38 "" +#define POST_STRING_0x39 "" +#define POST_STRING_0x3a "" +#define POST_STRING_0x3b "" +#define POST_STRING_0x3c "" +#define POST_STRING_0x3d "" +#define POST_STRING_0x3e "" +#define POST_STRING_0x3f "" +#define POST_STRING_0x40 "" +#define POST_STRING_0x41 "" +#define POST_STRING_0x42 "" +#define POST_STRING_0x43 "" +#define POST_STRING_0x44 "" +#define POST_STRING_0x45 "" +#define POST_STRING_0x46 "" +#define POST_STRING_0x47 "" +#define POST_STRING_0x48 "" +#define POST_STRING_0x49 "" +#define POST_STRING_0x4a "" +#define POST_STRING_0x4b "" +#define POST_STRING_0x4c "" +#define POST_STRING_0x4d "" +#define POST_STRING_0x4e "" +#define POST_STRING_0x4f "" +#define POST_STRING_0x50 "" +#define POST_STRING_0x51 "" +#define POST_STRING_0x52 "" +#define POST_STRING_0x53 "" +#define POST_STRING_0x54 "" +#define POST_STRING_0x55 "" +#define POST_STRING_0x56 "" +#define POST_STRING_0x57 "" +#define POST_STRING_0x58 "" +#define POST_STRING_0x59 "" +#define POST_STRING_0x5a "" +#define POST_STRING_0x5b "" +#define POST_STRING_0x5c "" +#define POST_STRING_0x5d "" +#define POST_STRING_0x5e "" +#define POST_STRING_0x5f "" +#define POST_STRING_0x60 "" +#define POST_STRING_0x61 "" +#define POST_STRING_0x62 "" +#define POST_STRING_0x63 "" +#define POST_STRING_0x64 "" +#define POST_STRING_0x65 "" +#define POST_STRING_0x66 "" +#define POST_STRING_0x67 "" +#define POST_STRING_0x68 "" +#define POST_STRING_0x69 "" +#define POST_STRING_0x6a "" +#define POST_STRING_0x6b "" +#define POST_STRING_0x6c "" +#define POST_STRING_0x6d "" +#define POST_STRING_0x6e "" +#define POST_STRING_0x6f "" +#define POST_STRING_0x70 "Before Device Probe" +#define POST_STRING_0x71 "Initializing Chips" +#define POST_STRING_0x72 "Starting Device Enumeration" +#define POST_STRING_0x73 "Device Resource Allocation" +#define POST_STRING_0x74 "Device Enable" +#define POST_STRING_0x75 "Device Initialization" +#define POST_STRING_0x76 "After Device Probe" +#define POST_STRING_0x77 "OS Resume Check" +#define POST_STRING_0x78 "OS Resume" +#define POST_STRING_0x79 "Write Tables" +#define POST_STRING_0x7a "Load Payload" +#define POST_STRING_0x7b "Boot Payload" +#define POST_STRING_0x7c "" +#define POST_STRING_0x7d "" +#define POST_STRING_0x7e "" +#define POST_STRING_0x7f "" +#define POST_STRING_0x80 "" +#define POST_STRING_0x81 "" +#define POST_STRING_0x82 "" +#define POST_STRING_0x83 "" +#define POST_STRING_0x84 "" +#define POST_STRING_0x85 "" +#define POST_STRING_0x86 "" +#define POST_STRING_0x87 "" +#define POST_STRING_0x88 "Before calling FSP Notify (end of firmware)" +#define POST_STRING_0x89 "After calling FSP Notify (end of firmware)" +#define POST_STRING_0x8a "" +#define POST_STRING_0x8b "" +#define POST_STRING_0x8c "" +#define POST_STRING_0x8d "" +#define POST_STRING_0x8e "" +#define POST_STRING_0x8f "" +#define POST_STRING_0x90 "Before calling FSP TempRamInit" +#define POST_STRING_0x91 "" +#define POST_STRING_0x92 "" +#define POST_STRING_0x93 "" +#define POST_STRING_0x94 "" +#define POST_STRING_0x95 "" +#define POST_STRING_0x96 "" +#define POST_STRING_0x97 "" +#define POST_STRING_0x98 "" +#define POST_STRING_0x99 "" +#define POST_STRING_0x9a "" +#define POST_STRING_0x9b "" +#define POST_STRING_0x9c "" +#define POST_STRING_0x9d "" +#define POST_STRING_0x9e "" +#define POST_STRING_0x9f "" +#define POST_STRING_0xa0 "" +#define POST_STRING_0xa1 "" +#define POST_STRING_0xa2 "" +#define POST_STRING_0xa3 "" +#define POST_STRING_0xa4 "" +#define POST_STRING_0xa5 "" +#define POST_STRING_0xa6 "" +#define POST_STRING_0xa7 "" +#define POST_STRING_0xa8 "" +#define POST_STRING_0xa9 "" +#define POST_STRING_0xaa "" +#define POST_STRING_0xab "" +#define POST_STRING_0xac "" +#define POST_STRING_0xad "" +#define POST_STRING_0xae "" +#define POST_STRING_0xaf "" +#define POST_STRING_0xb0 "" +#define POST_STRING_0xb1 "" +#define POST_STRING_0xb2 "" +#define POST_STRING_0xb3 "" +#define POST_STRING_0xb4 "" +#define POST_STRING_0xb5 "" +#define POST_STRING_0xb6 "" +#define POST_STRING_0xb7 "" +#define POST_STRING_0xb8 "" +#define POST_STRING_0xb9 "" +#define POST_STRING_0xba "" +#define POST_STRING_0xbb "" +#define POST_STRING_0xbc "" +#define POST_STRING_0xbd "" +#define POST_STRING_0xbe "" +#define POST_STRING_0xbf "" +#define POST_STRING_0xc0 "" +#define POST_STRING_0xc1 "" +#define POST_STRING_0xc2 "" +#define POST_STRING_0xc3 "" +#define POST_STRING_0xc4 "" +#define POST_STRING_0xc5 "" +#define POST_STRING_0xc6 "" +#define POST_STRING_0xc7 "" +#define POST_STRING_0xc8 "" +#define POST_STRING_0xc9 "" +#define POST_STRING_0xca "" +#define POST_STRING_0xcb "" +#define POST_STRING_0xcc "" +#define POST_STRING_0xcd "" +#define POST_STRING_0xce "" +#define POST_STRING_0xcf "" +#define POST_STRING_0xd0 "" +#define POST_STRING_0xd1 "" +#define POST_STRING_0xd2 "" +#define POST_STRING_0xd3 "" +#define POST_STRING_0xd4 "" +#define POST_STRING_0xd5 "" +#define POST_STRING_0xd6 "" +#define POST_STRING_0xd7 "" +#define POST_STRING_0xd8 "" +#define POST_STRING_0xd9 "" +#define POST_STRING_0xda "" +#define POST_STRING_0xdb "" +#define POST_STRING_0xdc "" +#define POST_STRING_0xdd "" +#define POST_STRING_0xde "" +#define POST_STRING_0xdf "" +#define POST_STRING_0xe0 "" +#define POST_STRING_0xe1 "" +#define POST_STRING_0xe2 "" +#define POST_STRING_0xe3 "RAM Failure" +#define POST_STRING_0xe4 "" +#define POST_STRING_0xe5 "" +#define POST_STRING_0xe6 "" +#define POST_STRING_0xe7 "" +#define POST_STRING_0xe8 "" +#define POST_STRING_0xe9 "" +#define POST_STRING_0xea "" +#define POST_STRING_0xeb "" +#define POST_STRING_0xec "" +#define POST_STRING_0xed "" +#define POST_STRING_0xee "" +#define POST_STRING_0xef "" +#define POST_STRING_0xf0 "" +#define POST_STRING_0xf1 "" +#define POST_STRING_0xf2 "" +#define POST_STRING_0xf3 "" +#define POST_STRING_0xf4 "" +#define POST_STRING_0xf5 "" +#define POST_STRING_0xf6 "" +#define POST_STRING_0xf7 "" +#define POST_STRING_0xf8 "" +#define POST_STRING_0xf9 "" +#define POST_STRING_0xfa "" +#define POST_STRING_0xfb "" +#define POST_STRING_0xfc "" +#define POST_STRING_0xfd "" +#define POST_STRING_0xfe "" +#define POST_STRING_0xff "" + #endif /* POST_CODES_H */ diff --git a/src/console/Kconfig b/src/console/Kconfig index c6aec18..acfd842 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -537,6 +537,15 @@ initialization can happen. This option suppresses all postcodes in the early assembly code. +config POSTCODE_DATA_IN_CBFS + bool "Save POST code data in CBFS" + depends on !NO_POST + help + Save information about the POST codes in CBFS for parser + access. This will create a list of POST codes used by this coreboot + build, which stages they're in, and a brief bit of text about the + code. + config HWBASE_DEBUG_CB bool default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 diff --git a/src/console/post.c b/src/console/post.c index f3a1463..e20a26a 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -12,7 +12,7 @@ */ void __weak mainboard_post(uint8_t value) { } -void post_code(uint8_t value) +void _post_code(uint8_t value) { if (!CONFIG(NO_POST)) { /* Assume this to be the most reliable and simplest type diff --git a/src/include/console/console.h b/src/include/console/console.h index 6f44d7f..1ea3aad 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -6,6 +6,7 @@ #include <commonlib/console/post_codes.h> #include <console/vtxprintf.h> #include <stdint.h> +#include <rules.h> /* console.h is supposed to provide the log levels defined in here: */ #include <commonlib/loglevel.h> /* IWYU pragma: export */ @@ -13,14 +14,46 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) -void post_code(u8 value); + + +void _post_code(u8 value); void mainboard_post(u8 value); void arch_post_code(u8 value); void soc_post_code(uint8_t value); +#define POST_CODE_INIT_ATTR __attribute__((used, section(".post_code"))) + +struct post_code_entry { + uint8_t val; + uint8_t pad[15]; // just for testing, this gives a nice layout + const char text[64]; + const char stage[16]; +}; + +#if CONFIG(POSTCODE_DATA_IN_CBFS) +#define GEN_POST_CODE_ENTRY(VALUE) \ + static struct post_code_entry POST_CODE_INIT_ATTR POSTCODE_## VALUE = \ + { \ + .val = VALUE, \ + .text = POST_STRING_## VALUE, \ + .stage = ENV_STRING, \ + }; \ +#else +#define GEN_POST_CODE_ENTRY(VALUE) +#endif + +#define post_code(PC) \ + { \ + GEN_POST_CODE_ENTRY(PC) \ + _post_code(PC); \ + } + void __noreturn die(const char *fmt, ...); -#define die_with_post_code(value, fmt, ...) \ - do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0) +#define die_with_post_code(value, fmt, ...) \ + { \ + GEN_POST_CODE_ENTRY(value) \ + do { _post_code(value); die(fmt, ##__VA_ARGS__); } while (0); \ + } /* * This function is weak and can be overridden to provide additional diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 714452d..0e3c335 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -49,7 +49,6 @@ struct boot_state { const char *name; boot_state_t id; - u8 post_code; struct boot_phase phases[2]; boot_state_t (*run_state)(void *arg); void *arg; @@ -61,7 +60,6 @@ { \ .name = #state_, \ .id = state_, \ - .post_code = POST_ ## state_, \ .phases = { { NULL, 0 }, { NULL, 0 } }, \ .run_state = run_func_, \ .arg = NULL, \ @@ -315,6 +313,50 @@ .seq = BS_ON_ENTRY, }; +static void bs_post_code(boot_state_t id) +{ + switch (id) { + case BS_PRE_DEVICE: + post_code(POST_BS_PRE_DEVICE); + break; + case BS_DEV_INIT_CHIPS: + post_code(POST_BS_DEV_INIT_CHIPS); + break; + case BS_DEV_ENUMERATE: + post_code(POST_BS_DEV_ENUMERATE); + break; + case BS_DEV_RESOURCES: + post_code(POST_BS_DEV_RESOURCES); + break; + case BS_DEV_ENABLE: + post_code(POST_BS_DEV_ENABLE); + break; + case BS_DEV_INIT: + post_code(POST_BS_DEV_INIT); + break; + case BS_POST_DEVICE: + post_code(POST_BS_POST_DEVICE); + break; + case BS_OS_RESUME_CHECK: + post_code(POST_BS_OS_RESUME_CHECK); + break; + case BS_OS_RESUME: + post_code(POST_BS_OS_RESUME); + break; + case BS_WRITE_TABLES: + post_code(POST_BS_WRITE_TABLES); + break; + case BS_PAYLOAD_LOAD: + post_code(POST_BS_PAYLOAD_LOAD); + break; + case BS_PAYLOAD_BOOT: + post_code(POST_BS_PAYLOAD_BOOT); + break; + default: + printk(BIOS_ERR, "Unknown boot-state\n"); + }; +} + static void bs_walk_state_machine(void) { @@ -346,7 +388,7 @@ bs_sample_time(state); - post_code(state->post_code); + bs_post_code(state->id); next_id = state->run_state(state->arg); -- To view, visit https://review.coreboot.org/c/coreboot/+/71708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b6e79a29235baaff7b744ab1c97ddaf64af391 Gerrit-Change-Number: 71708 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2023