coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

1 participants
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[M] Change in coreboot[master]: soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of...
by Nico Huber (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Sean Rhodes, Angel Pons, Arthur Heymans, Andrey Petrov. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66244 ) Change subject: soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONF ...................................................................... Patch Set 20: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/66244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b Gerrit-Change-Number: 66244 Gerrit-PatchSet: 20 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 11:07:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
by Nico Huber (Code Review) 05 Sep '22

05 Sep '22

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52873 ) Change subject: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: This is quite interesting. Is it a silicon bug, i.e. it really disables i/o if the bus master bit is cleared? Or does the PMC actually need bus master requests to do what the i/o triggers? -- To view, visit https://review.coreboot.org/c/coreboot/+/52873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Gerrit-Change-Number: 52873 Gerrit-PatchSet: 7 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 11:01:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: qualcomm/sc7280: remove unnecessary malloc and early return on failure
by Vinod Polimera (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Shelley Chen, Venkat Thogaru, Julius Werner, Yu-Ping Wu. Vinod Polimera has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66975 ) Change subject: qualcomm/sc7280: remove unnecessary malloc and early return on failure ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66975/comment/3fe1d43b_0dd8b25f PS2, Line 6: > > Possible long commit subject (prefer a maximum 65 characters) […] Done https://review.coreboot.org/c/coreboot/+/66975/comment/37a8e30f_58a6b88e PS2, Line 9: priniting > printing Done https://review.coreboot.org/c/coreboot/+/66975/comment/ae142daf_c382d6b7 PS2, Line 11: static > It's not a static variable, just a local variable. Done File src/soc/qualcomm/sc7280/display/edp_ctrl.c: https://review.coreboot.org/c/coreboot/+/66975/comment/3204d637_f8496ef5 PS2, Line 1225: tu_table > Align with BIOS_INFO. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/66975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426 Gerrit-Change-Number: 66975 Gerrit-PatchSet: 3 Gerrit-Owner: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 10:52:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
by Nico Huber (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Martin L Roth, Jakub Czapiga, Arthur Heymans, Patrick Rudolph, Elyes Haouas. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62181 ) Change subject: device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4} ...................................................................... Patch Set 8: Code-Review+1 (3 comments) File src/device/dram/ddr3.c: https://review.coreboot.org/c/coreboot/+/62181/comment/4f2914d0_6951521b PS7, Line 549: dimm->mod_type = SPD_UNDEFINED; > Given that `SPD_UNDEFINED == 0`, the whole `if` does the same as a simple […] Done File src/device/dram/ddr4.c: https://review.coreboot.org/c/coreboot/+/62181/comment/e50e91db_a9f2180f PS7, Line 303: dimm->mod_type = SPD_UNDEFINED; > Same here. Done File src/include/device/dram/ddr4.h: https://review.coreboot.org/c/coreboot/+/62181/comment/861e9dff_c6ed3082 PS7, Line 29: SPD_DDR4_DIMM_TYPE_EXTENDED = 0x0, > defined here: src/include/spd. […] Don't know what you mean is defined there. This _TYPE_EXTENDED seems to be omitted there. I looked into the spec now. A 0 in the SPD would mean the type is specified somewhere else (byte 15). We currently use the enum as if it's the only information needed. So I'd say it's ok to omit this special register value. However, we might want to remove the SPD_DDR*_DIMM_TYPE_MASK entries too, as those are also about register values. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/62181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621 Gerrit-Change-Number: 62181 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 05 Sep 2022 10:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Modify fan speed/duty table
by Dtrain Hsu (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang. Hello build bot (Jenkins), Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67307 to look at the new patch set (#3). Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table ...................................................................... mb/google/brya/var/kinox: Modify fan speed/duty table Modify fan speed/duty table follow "Duty table.xlsx". The table has 20 elements so sets the DPTF_MAX_FAN_PERF_STATES from 10 to 20. BUG=b:244262869 TEST=Boot to ChromeOS. Using SDV system, enter duty vaule,and then system feedback fan speed. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 --- M src/include/acpi/acpigen_dptf.h M src/mainboard/google/brya/variants/kinox/overridetree.cb 2 files changed, 38 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/67307/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/67307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Gerrit-Change-Number: 67307 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Modify fan speed/duty table
by Dtrain Hsu (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67307 ) Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67307/comment/3730e5c4_1a325abe PS2, Line 209: [10] = { 45, 2566, 0, 0, }, : [11] = { 43, 2415, 0, 0, }, : [12] = { 40, 2010, 0, 0, }, : [13] = { 36, 1813, 0, 0, }, : [14] = { 35, 1686, 0, 0, }, : [15] = { 32, 1404, 0, 0, }, : [16] = { 30, 1160, 0, 0, }, : [17] = { 20, 760, 0, 0, }, : [18] = { 10, 760, 0, 0, }, : [19] = { 0, 0, 0, 0, } > How did you verify these values working on the system as per above changes ? […] ODM thermal team replied in b/244262869#comment9. -- To view, visit https://review.coreboot.org/c/coreboot/+/67307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Gerrit-Change-Number: 67307 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 10:40:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/kinox: Update the DPTF parameters and fan table
by Dtrain Hsu (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67314 ) Change subject: mb/google/brya/var/kinox: Update the DPTF parameters and fan table ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67314/comment/6bf3cae4_7c3f55de PS2, Line 160: 97 > Any reason for these Critical temperature values change ? Did you observe that system is hitting the […] From ODM thermal team. (b/244657172#comment14) Hi Summent The system can not hit the 93C. We can change the vaule because the vaule is common 95C in previous projects Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/67314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e Gerrit-Change-Number: 67314 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 10:37:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/broadwell: Consolidate SPD handling
by Nico Huber (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55811 ) Change subject: soc/intel/broadwell: Consolidate SPD handling ...................................................................... Patch Set 14: (1 comment) File src/mainboard/intel/wtm2/pei_data.c: https://review.coreboot.org/c/coreboot/+/55811/comment/417b7bf2_2eeb9717 PS14, Line 8: spdi->addresses[0] = 0x51; : spdi->addresses[2] = 0x51; > looks like there is a typo. I couldn't find information about WTM2. It could be an error and maybe wasn't noticed because it works when both slots have compatible DIMMs plugged in. > Is it possible the have same address for both dimms ? Not for DIMMs. But it's possible to have the same chips attached to both channels (e.g. when DRAM is soldered down) and a single EEPROM for the common configuration (and yes, sometimes soldered down DRAM comes with an EEPROM *shrug*). -- To view, visit https://review.coreboot.org/c/coreboot/+/55811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10 Gerrit-Change-Number: 55811 Gerrit-PatchSet: 14 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 10:28:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Alderlake P in inteltool
by Kacper Stojek (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Kacper Stojek, Michał Kopeć, Stefan Reinauer, Angel Pons. Hello build bot (Jenkins), Michał Kopeć, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66825 to look at the new patch set (#7). Change subject: util/inteltool: Add support for Alderlake P in inteltool ...................................................................... util/inteltool: Add support for Alderlake P in inteltool TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Signed-off-by: Kacper Stojek <kacper.stojek(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/alderlake_p.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 708 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/66825/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/66825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Gerrit-Change-Number: 66825 Gerrit-PatchSet: 7 Gerrit-Owner: Kacper Stojek Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kacper Stojek Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: qualcomm/sc7280: remove unnecessary malloc and early return on failure
by Venkat Thogaru (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Shelley Chen, Venkat Thogaru, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66975 to look at the new patch set (#3). Change subject: qualcomm/sc7280: remove unnecessary malloc and early return on failure ...................................................................... qualcomm/sc7280: remove unnecessary malloc and early return on failure Instead of just printing the fatal errors, do early return so that boot up time will be reduced during display init failure. Remove malloc allocation and make tu a local variable. Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426 Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> --- M src/soc/qualcomm/sc7280/display/edp_ctrl.c 1 file changed, 160 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/66975/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/66975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426 Gerrit-Change-Number: 66975 Gerrit-PatchSet: 3 Gerrit-Owner: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2022