coreboot-gerrit April 2022

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Change in coreboot[master]: drivers/intel/dptf: Add support for Battery participant
by Eric Lai (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Varshit B Pandya, Lance Zhao, Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63315 ) Change subject: drivers/intel/dptf: Add support for Battery participant ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Will this duplicate from EC BAT0? -- To view, visit https://review.coreboot.org/c/coreboot/+/63315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Gerrit-Change-Number: 63315 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 02 Apr 2022 11:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add HID for DPTF Battery Participant
by Eric Lai (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63316 ) Change subject: soc/intel/alderlake: Add HID for DPTF Battery Participant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 Gerrit-Change-Number: 63316 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 02 Apr 2022 11:01:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure PAVP at compile-time
by Felix Singer (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Christian Walter, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Arthur Heymans, Lean Sheng Tan. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63304 ) Change subject: soc/intel/alderlake: Configure PAVP at compile-time ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63304/comment/68fe6148_c8a9221a PS1, Line 7: Configure PAVP at compile-time Suggestion: Hook up PAVP to Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/63304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6 Gerrit-Change-Number: 63304 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 02 Apr 2022 10:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add HID for DPTF Battery Participant
by Varshit B Pandya (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Tim Wawrzynczak. Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63316 ) Change subject: soc/intel/alderlake: Add HID for DPTF Battery Participant ...................................................................... soc/intel/alderlake: Add HID for DPTF Battery Participant BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 --- M src/soc/intel/alderlake/dptf.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63316/1 diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c index 59243ba..7016d8c 100644 --- a/src/soc/intel/alderlake/dptf.c +++ b/src/soc/intel/alderlake/dptf.c @@ -14,6 +14,8 @@ .tpch_device_hid = "INTC1049", /* _HID for the toplevel TPWR device, typically \_SB.DPTF.TPWR */ .tpwr_device_hid = "INTC1060", + /* _HID for the toplevel BAT1 device, typically \_SB.DPTF.BAT1 */ + .tbat_device_hid = "INTC1061", .tpch_method_names = { .set_fivr_low_clock_method = "RFC0", -- To view, visit https://review.coreboot.org/c/coreboot/+/63316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 Gerrit-Change-Number: 63316 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Add support for Battery participant
by Varshit B Pandya (Code Review) 02 Apr '22

02 Apr '22

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63315 ) Change subject: drivers/intel/dptf: Add support for Battery participant ...................................................................... drivers/intel/dptf: Add support for Battery participant As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for BAT1 device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check BAT1 device Device (BAT1) { Name (_HID, "INTC1061") // _HID: Hardware ID Name (_UID, "BAT1") // _UID: Unique ID Name (_STR, "Battery Participant") // _STR: Description String Name (PTYP, 0xC) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/include/acpi/acpigen_dptf.h 5 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63315/1 diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 4a5bd09..ea608b8 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -76,6 +76,8 @@ return "TPCH"; case DPTF_POWER: return "TPWR"; + case DPTF_BATTERY: + return "BAT1"; default: return ""; } diff --git a/src/drivers/intel/dptf/Kconfig b/src/drivers/intel/dptf/Kconfig index a7a5760..1420425 100644 --- a/src/drivers/intel/dptf/Kconfig +++ b/src/drivers/intel/dptf/Kconfig @@ -19,3 +19,10 @@ help When enabled, chip driver/intel/dptf will publish information to the SSDT for TPWR device. + +config DRIVERS_INTEL_DPTF_SUPPORTS_BAT + def_bool n + depends on DRIVERS_INTEL_DPTF + help + When enabled, chip driver/intel/dptf will publish information to the + SSDT for BAT1 device. diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index ecb338b..23df2d9 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -15,11 +15,13 @@ DPTF_GENERIC_PARTICIPANT_TYPE_TPCH = 0x5, DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER = 0xB, DPTF_GENERIC_PARTICIPANT_TYPE_POWER = 0x11, + DPTF_GENERIC_PARTICIPANT_TYPE_BATTERY = 0xC, }; #define DEFAULT_CHARGER_STR "Battery Charger" #define DEFAULT_TPCH_STR "Intel PCH FIVR Participant" #define DEFAULT_POWER_STR "Power Participant" +#define DEFAULT_BATTERY_STR "Battery Participant" #define PMC_IPC_COMMAND_FIVR_SIZE 0x8 @@ -388,6 +390,26 @@ write_create_tpwr(platform_info); } +static void write_create_tbat(const struct dptf_platform_info *platform_info) +{ + acpigen_write_device("BAT1"); + acpigen_write_name("_HID"); + if (platform_info->tbat_device_hid != NULL) + dptf_write_hid(platform_info->use_eisa_hids, platform_info->tbat_device_hid); + acpigen_write_name_string("_UID", "BAT1"); + acpigen_write_name_string("_STR", DEFAULT_BATTERY_STR); + acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_BATTERY); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_device_end(); /* BAT1 Battery Participant Device */ +} + + +static void write_tbat_methods(const struct dptf_platform_info *platform_info) +{ + write_create_tbat(platform_info); +} + + /* \_SB.DPTF - note: leaves the Scope open for child devices */ static void write_open_dptf_device(const struct device *dev, const struct dptf_platform_info *platform_info) @@ -429,6 +451,9 @@ if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPWR)) write_tpwr_methods(platform_info); + if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_BAT)) + write_tbat_methods(platform_info); + acpigen_pop_len(); /* DPTF Device (write_open_dptf_device) */ acpigen_pop_len(); /* Scope */ } diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h index c80e64a..ed25880 100644 --- a/src/drivers/intel/dptf/dptf.h +++ b/src/drivers/intel/dptf/dptf.h @@ -16,6 +16,7 @@ const char *fan_hid; const char *tpch_device_hid; const char *tpwr_device_hid; + const char *tbat_device_hid; struct { const char *set_fivr_low_clock_method; const char *set_fivr_high_clock_method; diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 0d49452..893256e 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -27,6 +27,7 @@ DPTF_TEMP_SENSOR_4, DPTF_TPCH, DPTF_POWER, + DPTF_BATTERY, DPTF_PARTICIPANT_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Gerrit-Change-Number: 63315 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Upgrade IASL from 20211217 to 20220331
by Elyes Haouas (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63279 ) Change subject: crossgcc: Upgrade IASL from 20211217 to 20220331 ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Maybe also add, if you tested it with a board. No, not tested on hardware. -- To view, visit https://review.coreboot.org/c/coreboot/+/63279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d Gerrit-Change-Number: 63279 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sat, 02 Apr 2022 09:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Upgrade IASL from 20211217 to 20220331
by Elyes Haouas (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Martin Roth, Elyes Haouas. Hello build bot (Jenkins), Martin Roth, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63279 to look at the new patch set (#4). Change subject: crossgcc: Upgrade IASL from 20211217 to 20220331 ...................................................................... crossgcc: Upgrade IASL from 20211217 to 20220331 "REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is not needed any more as it’s included upstream. Changes: https://acpica.org/node/199 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d --- M Makefile.inc M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20220331_iasl.patch D util/crossgcc/sum/acpica-unix2-20211217.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20220331.tar.gz.cksum 5 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/63279/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d Gerrit-Change-Number: 63279 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add new CPU ID
by Paul Menzel (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Maulik V Vaghela, Christian Walter, Tim Wawrzynczak, Angel Pons, Meera Ravindranath, Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63302 ) Change subject: soc/intel/alderlake: Add new CPU ID ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3 Gerrit-Change-Number: 63302 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 02 Apr 2022 08:25:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update CPU IDs with correct steppings
by Paul Menzel (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Meera Ravindranath, Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63299 ) Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63299/comment/27b4ea3c_304ac033 PS2, Line 9: Update ADL CPU IDs per correct steppings. Please mention the source. -- To view, visit https://review.coreboot.org/c/coreboot/+/63299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Gerrit-Change-Number: 63299 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 02 Apr 2022 08:25:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superiotool/ite: add IT8265E EC registers
by Michał Kopeć (Code Review) 02 Apr '22

02 Apr '22

Attention is currently required from: Michał Żygowski, Paul Menzel, Felix Held. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63310 ) Change subject: superiotool/ite: add IT8265E EC registers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63310/comment/127a18a0_b37b4577 PS1, Line 7: superiotool/ite.c > superiotool/ite Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Gerrit-Change-Number: 63310 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 02 Apr 2022 08:21:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022