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Hello build bot (Jenkins), Michał Żygowski, Paul Menzel, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: superiotool/ite: add IT8265E EC registers
......................................................................
superiotool/ite: add IT8265E EC registers
Add support for dumping ITE IT8625E Environmental Controller registers.
Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".
Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/superiotool/ite.c
1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63310/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63306 )
Change subject: cbfs_image.c: Drop compatibility for old images
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63306/comment/34d1862b_a03ee504
PS1, Line 7: cbfs_image.c
cbfstool/cbfs_image
https://review.coreboot.org/c/coreboot/+/63306/comment/9217bb00_104dce31
PS1, Line 9: This has long been fixed.
What is “this”?
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Change subject: superiotool/ite.c: add IT8265E EC registers
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63310/comment/bc150e21_7ef38567
PS1, Line 7: superiotool/ite.c
superiotool/ite
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 )
Change subject: mb/google/brya: Disable PCH USB2 phy power gating
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Patch Set 4: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63294/comment/61d1215a_0b86849c
PS1, Line 9: The patch disables PCH USB2 Phy power gating.
> Added the motivation details.
Thanks. Fell free to mark these comments as resolved once you acted on them.
Commit Message:
https://review.coreboot.org/c/coreboot/+/63294/comment/64f47c08_3346550b
PS4, Line 10: to prevent possible display flicker issue
“possible” means it was never reproduced in practice and is theoretical, or it happens sometimes, and sometimes it does not?
https://review.coreboot.org/c/coreboot/+/63294/comment/f63b610b_223437b9
PS4, Line 9: The patch disables PCH USB2 Phy power gating. This change is required
: to prevent possible display flicker issue.
Shorter:
> Disable PCH USB2 PHY power gating to prevent display flickering … (in the OS?).
File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/63294/comment/e8fdf277_50f81ebd
PS4, Line 25: # Disable PCH USB2 Phy power gating
I see all the other entries have comments, but in this case the variable names are self-describing, so I’d remove the comment. I’d rather add the display flicker issue as a comment.
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Change subject: coreboot tables: Add PCIe info to coreboot table
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Patch Set 5:
(1 comment)
File payloads/libpayload/include/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/63251/comment/ae3ae6e6_0b38229b
PS4, Line 276: config_base
> It seems that config_base and ctrl_base are not the same thing, config_base is more like the registe […]
Ack
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Change subject: soc/amd/cezanne/fw.cfg: provide default SPL table binary
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Patch Set 2: Code-Review+2
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