coreboot-gerrit April 2022

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Change in coreboot[master]: qualcomm/sc7280: Add support for edp and mdp driver
by Shelley Chen (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Ravi Kumar Bokka. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62370 ) Change subject: qualcomm/sc7280: Add support for edp and mdp driver ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Ravi, can you abandon this and upload the changes to https://review.coreboot.org/c/coreboot/+/61342 ? That's where all the comments and older patches have been up until now. -- To view, visit https://review.coreboot.org/c/coreboot/+/62370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6368e3064548eaead5046b5ca6cd31e1fd498187 Gerrit-Change-Number: 62370 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 23:05:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases: Deprecate Intel Quark SoC
by Michael Niewöhner (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Felix Singer, Martin Roth, Paul Menzel, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63283 ) Change subject: Documentation/releases: Deprecate Intel Quark SoC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e437d363c90c5155d6723a4377dc6052e80ebe7 Gerrit-Change-Number: 63283 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 23:03:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Add strict flag to clock_configure()
by Shelley Chen (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Add strict flag to clock_configure() ...................................................................... Patch Set 5: (1 comment) File src/soc/qualcomm/sc7180/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/a38ed2f8_a2739fbd PS4, Line 218: &mdss_clk_cfg, 0, 0, false); > nit: looking at how this works (which is a little haphazard anyway... […] I think that if it's the case that we're going to universally look for exact matches, then we should actually change the common/clock.c comparison to be == instead at https://review.coreboot.org/c/coreboot/+/63289/5/src/soc/qualcomm/common/cl… ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 22:51:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica/port_descriptors: clean up variable names
by 9elements QA (Code Review) 01 Apr '22

01 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63261 ) Change subject: mb/amd/majolica/port_descriptors: clean up variable names ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98924 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98923 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98922 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98921 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/98920 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98919 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/98918 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98917 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98916 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98915 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98914 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98913 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98912 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98911 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98910 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98909 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I490111ecea84c934585d0bbd623486fba76eb7f1 Gerrit-Change-Number: 63261 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 22:50:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Add strict flag to clock_configure()
by Shelley Chen (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Add strict flag to clock_configure() ...................................................................... Patch Set 5: (2 comments) File src/soc/qualcomm/common/include/soc/clock_common.h: https://review.coreboot.org/c/coreboot/+/63289/comment/7c3e1ef5_3cb53451 PS4, Line 151: highest > nit: "higher"? Done File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/63d0617c_5413ea69 PS4, Line 311: false > I think that I definitely wanted to check for the SPI frequency but didn't want to screw up the othe […] Ok, turning these on did find a bug (CB:63311), so good call. -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 22:36:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: fix emmc and sd card clocks
by Shelley Chen (Code Review) 01 Apr '22

01 Apr '22

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63311 ) Change subject: herobrine: fix emmc and sd card clocks ...................................................................... herobrine: fix emmc and sd card clocks Found an issue where emmc and sd clocks were being misconfigured due to using incorrect integer values when called instead of the defined enums. Fixing by splitting the clock_configure_sdcc() function into two (sdcc1 and sdcc2) as there was no commonality between the two cases anyway. As a result, we can also get rid of the clk_sdcc enum. BUG=b:198627043 BRANCH=None TEST=build herobrine image and test in conjunction with CB:63289 make sure assert is not thrown. Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/clock.h 3 files changed, 42 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/63311/1 diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 7bdede0..c8af686 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -50,9 +50,9 @@ static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ - clock_configure_sdcc(1, 384 * MHz); + clock_configure_sdcc1(384 * MHz); /* Configure clock for SD card */ - clock_configure_sdcc(2, 50 * MHz); + clock_configure_sdcc2(50 * MHz); configure_sdhci(); gpi_firmware_load(QUP_0_GSI_BASE); diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 746035c..e321e8d 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -291,45 +291,46 @@ } } -void clock_configure_sdcc(enum clk_sdcc sdcc, uint32_t hz) +void clock_configure_sdcc1(uint32_t hz) { - if (sdcc == SDCC1_CLK) { - if (hz > CLK_100MHZ) { - struct alpha_pll_reg_val_config gpll10_cfg = {0}; - gpll10_cfg.reg_mode = &gcc->gpll10.mode; - gpll10_cfg.reg_opmode = &gcc->gpll10.opmode; - gpll10_cfg.reg_l = &gcc->gpll10.l; - gpll10_cfg.l_val = 0x14; - gpll10_cfg.reg_cal_l = &gcc->gpll10.cal_l; - gpll10_cfg.cal_l_val = 0x44; - gpll10_cfg.fsm_enable = true; - gpll10_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en; - clock_configure_enable_gpll(&gpll10_cfg, true, 9); - } - clock_configure((struct clock_rcg *)&gcc->sdcc1, sdcc1_core_cfg, - hz, ARRAY_SIZE(sdcc1_core_cfg)); - clock_enable(&gcc->sdcc1_ahb_cbcr); - clock_enable(&gcc->sdcc1_apps_cbcr); - } else if (sdcc == SDCC2_CLK) { - if (hz > CLK_100MHZ) { - struct alpha_pll_reg_val_config gpll9_cfg = {0}; - gpll9_cfg.reg_mode = &gcc->gpll9.mode; - gpll9_cfg.reg_opmode = &gcc->gpll9.opmode; - gpll9_cfg.reg_alpha = &gcc->gpll9.alpha; - gpll9_cfg.alpha_val = 0x1555; - gpll9_cfg.reg_l = &gcc->gpll9.l; - gpll9_cfg.l_val = 0x2A; - gpll9_cfg.reg_cal_l = &gcc->gpll9.cal_l; - gpll9_cfg.cal_l_val = 0x44; - gpll9_cfg.fsm_enable = true; - gpll9_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en; - clock_configure_enable_gpll(&gpll9_cfg, true, 8); - } - clock_configure((struct clock_rcg *)&gcc->sdcc2, sdcc2_core_cfg, - hz, ARRAY_SIZE(sdcc2_core_cfg)); - clock_enable(&gcc->sdcc2_ahb_cbcr); - clock_enable(&gcc->sdcc2_apps_cbcr); + if (hz > CLK_100MHZ) { + struct alpha_pll_reg_val_config gpll10_cfg = {0}; + gpll10_cfg.reg_mode = &gcc->gpll10.mode; + gpll10_cfg.reg_opmode = &gcc->gpll10.opmode; + gpll10_cfg.reg_l = &gcc->gpll10.l; + gpll10_cfg.l_val = 0x14; + gpll10_cfg.reg_cal_l = &gcc->gpll10.cal_l; + gpll10_cfg.cal_l_val = 0x44; + gpll10_cfg.fsm_enable = true; + gpll10_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en; + clock_configure_enable_gpll(&gpll10_cfg, true, 9); } + clock_configure((struct clock_rcg *)&gcc->sdcc1, sdcc1_core_cfg, + hz, ARRAY_SIZE(sdcc1_core_cfg)); + clock_enable(&gcc->sdcc1_ahb_cbcr); + clock_enable(&gcc->sdcc1_apps_cbcr); +} + +void clock_configure_sdcc2(uint32_t hz) +{ + if (hz > CLK_100MHZ) { + struct alpha_pll_reg_val_config gpll9_cfg = {0}; + gpll9_cfg.reg_mode = &gcc->gpll9.mode; + gpll9_cfg.reg_opmode = &gcc->gpll9.opmode; + gpll9_cfg.reg_alpha = &gcc->gpll9.alpha; + gpll9_cfg.alpha_val = 0x1555; + gpll9_cfg.reg_l = &gcc->gpll9.l; + gpll9_cfg.l_val = 0x2A; + gpll9_cfg.reg_cal_l = &gcc->gpll9.cal_l; + gpll9_cfg.cal_l_val = 0x44; + gpll9_cfg.fsm_enable = true; + gpll9_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en; + clock_configure_enable_gpll(&gpll9_cfg, true, 8); + } + clock_configure((struct clock_rcg *)&gcc->sdcc2, sdcc2_core_cfg, + hz, ARRAY_SIZE(sdcc2_core_cfg)); + clock_enable(&gcc->sdcc2_ahb_cbcr); + clock_enable(&gcc->sdcc2_apps_cbcr); } void clock_configure_dfsr(int qup) diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h index 744734e..d22ba37 100644 --- a/src/soc/qualcomm/sc7280/include/soc/clock.h +++ b/src/soc/qualcomm/sc7280/include/soc/clock.h @@ -272,11 +272,6 @@ int vote_bit; }; -enum clk_sdcc { - SDCC1_CLK, - SDCC2_CLK, -}; - enum clk_qup { QUP_WRAP0_S0, QUP_WRAP0_S1, @@ -385,7 +380,8 @@ void clock_init(void); void clock_configure_qspi(uint32_t hz); void clock_enable_qup(int qup); -void clock_configure_sdcc(enum clk_sdcc, uint32_t hz); +void clock_configure_sdcc1(uint32_t hz); +void clock_configure_sdcc2(uint32_t hz); void clock_configure_dfsr(int qup); int clock_enable_gdsc(enum clk_gdsc gdsc_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/63311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Gerrit-Change-Number: 63311 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/common: Add strict flag to clock_configure()
by Shelley Chen (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Julius Werner. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63289 to look at the new patch set (#5). Change subject: soc/qualcomm/common: Add strict flag to clock_configure() ...................................................................... soc/qualcomm/common: Add strict flag to clock_configure() When strict parameter is set to true, clock_configure() will try to find an exact match to the clock frequency given. If exact match cannot be found, then will throw an assertion error. BUG=b:198627043 BRANCH=None TEST=build herobrine image and try to set SPI frequency to number not supported. Ensure device doesn't boot. Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7280/clock.c 4 files changed, 30 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63289/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/dell/snb_ivb_workstations: Choose correct PCH for OptiPlex 9010
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63207 ) Change subject: mb/dell/snb_ivb_workstations: Choose correct PCH for OptiPlex 9010 ...................................................................... mb/dell/snb_ivb_workstations: Choose correct PCH for OptiPlex 9010 The Dell OptiPlex 9010 uses a Q77 PCH, which is Panther Point. The only difference is the definition of the `CROS_GPIO_DEVICE_NAME` macro, which is not used for non-ChromeOS coreboot builds. Change-Id: I7ad07b464aef24f7749c3fe9300b7f7dd865e47b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63207 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/dell/snb_ivb_workstations/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig.name b/src/mainboard/dell/snb_ivb_workstations/Kconfig.name index 1176f6a..6f6d833 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig.name @@ -1,7 +1,7 @@ config BOARD_DELL_OPTIPLEX_9010 bool "OptiPlex 9010 SFF" select BOARD_DELL_SNB_IVB_WORKSTATIONS - select SOUTHBRIDGE_INTEL_BD82X6X + select SOUTHBRIDGE_INTEL_C216 config BOARD_DELL_PRECISION_T1650 bool "Dell Precision T1650" -- To view, visit https://review.coreboot.org/c/coreboot/+/63207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ad07b464aef24f7749c3fe9300b7f7dd865e47b Gerrit-Change-Number: 63207 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63206 ) Change subject: mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports ...................................................................... mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe ports The PCH's PCIe ports do not support Gen3 speeds, only Gen1/Gen2. Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63206 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb index 30167f9..bfe453f 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb @@ -4,7 +4,7 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "sata_port_map" = "0x7" device pci 1c.4 on # PCIe Port #5 - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X" end device pci 1c.5 on end # PCIe Port #6 device pci 1c.6 on end # PCIe Port #7 diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb index 9452279..81133ee 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb @@ -5,10 +5,10 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "sata_port_map" = "0xf" device pci 1c.2 on # PCIe Port #3 - smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X" + smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X" end device pci 1c.4 on # PCIe Port #5 - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X" end device pci 1c.5 on end # PCIe Port #6 device pci 1c.6 on end # PCIe Port #7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6 Gerrit-Change-Number: 63206 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Disable legacy_8254_timer by default
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61861 ) Change subject: mb/starlabs/labtop: Disable legacy_8254_timer by default ...................................................................... mb/starlabs/labtop: Disable legacy_8254_timer by default It was enabled due to known compatibility issues with Qubes OS. Since the release of R4.1.0, this issue is no longer present so it can be disabled. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Iab6048dc93112b9365f0c2b46225569073eb32f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61861 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/labtop/cmos.default 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Angel Pons: Looks good to me, approved Andy Pont: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default index 0b83cb7..0783adf 100644 --- a/src/mainboard/starlabs/labtop/cmos.default +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -12,7 +12,7 @@ wireless=Enable webcam=Enable microphone=Enable -legacy_8254_timer=Enable +legacy_8254_timer=Disable usb_always_on=Disable thunderbolt=Disable # EC 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6048dc93112b9365f0c2b46225569073eb32f3 Gerrit-Change-Number: 61861 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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