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Change subject: soc/amd/cezanne: Allow to specify SPL table path in Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/61837/comment/35335888_3b257ac8
PS4, Line 382: default n
> i'd say that this kconfig option isn't needed and should be removed in a follow-up patch. […]
before CB:61836 broke that code path, the majolica image included the spl table. fixes are in CB:63314 and CB:61896
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Change subject: soc/amd/sabrina: Build support to add SPL File
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
see CB:63314 for a amdfwtool fix and the bugtracker for an updated fw.cfg file
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Change subject: soc/amd/cezanne/fw.cfg: provide default SPL table binary
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/61896/comment/96ba150b_019cc438
PS1, Line 380: HAVE_SPL_FILE
> yes. […]
after looking a bit more closely into this, the HAVE_SPL_FILE option should be kept, but not this patch adds the default to the fw.cfg file which should fix Majolica together with the amdfwtool fix that fixes the logic handling this
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Hello build bot (Jenkins), Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61896
to look at the new patch set (#2).
Change subject: soc/amd/cezanne/fw.cfg: provide default SPL table binary
......................................................................
soc/amd/cezanne/fw.cfg: provide default SPL table binary
Chause doesn't get to x86 bootblock without the SPL table binary, so I
assume that Majolica won't get to x86 bootblock too, since the Cezanne
default is not to include any SPL table binary. Fix this by adding the
SPL table file back to the fw.cfg file.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff
---
M src/soc/amd/cezanne/fw.cfg
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/61896/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61836 )
Change subject: amdfwtool: Add options to support mainboard specific SPL table
......................................................................
Patch Set 4:
(1 comment)
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/61836/comment/86f36a53_9552ebb5
PS4, Line 286: if (cb_config->have_mb_spl) {
: fw_type = AMD_FW_SPL;
: subprog = 0;
: } else {
: fw_type = AMD_FW_SKIP;
: }
this breaks the default !cb_config->have_mb_spl case. fix is in CB:63314
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Change subject: ChromeOS: Drop filling ECFW_RW/RO state in CNVS
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Patch Set 1: Code-Review+2
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Change subject: ChromeOS: Add legacy mainboard_ec_running_ro()
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Patch Set 14: Code-Review+2
(1 comment)
Patchset:
PS14:
> I had a followup prepared already, I can squash these together […]
Yeah I mean you're just adding a bunch of code in this patch now that you're removing again in the next one, I think squashing would make sense. But not that important as long as we end up where we want to end up.
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Change subject: soc/amd/sabrina: Build support to add SPL File
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
File src/soc/amd/sabrina/Kconfig:
https://review.coreboot.org/c/coreboot/+/63313/comment/f4619ca0_25fe4b69
PS1, Line 392: default n
seems that this default results in a non booting image; i don't want to introduce an option that only has one working value
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