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Hello Reka Norman, Rob Barnes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63317
to look at the new patch set (#2).
Change subject: util/cbmem: add type cast
......................................................................
util/cbmem: add type cast
arch_convert_raw_ts_entry returns a uint64_t, which needs to be cast
on ARM systems to avoid a type error.
BUG=b/227871959
TEST=no build errors in downstream
Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com>
Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b
---
M util/cbmem/cbmem.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63317/2
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Gerrit-Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b
Gerrit-Change-Number: 63317
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Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63317 )
Change subject: util/cbmem: add type cast
......................................................................
util/cbmem: add type cast
arch_convert_raw_ts_entry returns a uint64_t, which needs to be cast
on ARM systems to avoid a type error.
BUG=b/227871959
TEST=no build errors in downstream
Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com>
Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b
---
M util/cbmem/cbmem.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63317/1
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index 5b969e4..0dda151 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -639,7 +639,7 @@
}
if (last_part)
printf("%s", last_part);
- printf(" %lu\n", arch_convert_raw_ts_entry(stamp));
+ printf(" %lu\n", (long long)arch_convert_raw_ts_entry(stamp));
}
enum timestamps_print_type {
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63303 )
Change subject: soc/intel/alderlake: Add VrPowerDeliveryDesign to chip options
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63303/comment/ae1f3652_4b801d98
PS1, Line 7: Add VrPowerDeliveryDesign to chip options
Suggestion:
Hook up VrPowerDeliveryDesign to devicetree
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Change subject: arch/x86/postcar: Set up postcar MTRR in C code
......................................................................
Patch Set 11:
(3 comments)
File src/arch/x86/postcar.c:
https://review.coreboot.org/c/coreboot/+/54299/comment/f17092ea_6acd91b9
PS11, Line 3: #include <cpu/x86/msr.h>
u can put this in order, rest looks good.
File src/cpu/x86/mtrr/earlymtrr.c:
https://review.coreboot.org/c/coreboot/+/54299/comment/04520047_26ab6207
PS11, Line 126: for (int i = 0; i < ctx->max_var_mtrrs; i++) {
: wrmsr(MTRR_PHYS_BASE(i), zero);
: wrmsr(MTRR_PHYS_MASK(i), zero);
: }
can't u use clear_all_var_mtrr() here ?
https://review.coreboot.org/c/coreboot/+/54299/comment/002e6140_6cd5ef72
PS11, Line 131: wrmsr(MTRR_PHYS_BASE(i), ctx->mtrr[i].base);
: wrmsr(MTRR_PHYS_MASK(i), ctx->mtrr[i].mask);
set_var_mtrr() may be ?
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Change subject: drivers/intel/dptf: Add support for Battery participant
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
And why not DPTF driver read from kernel directly? Battery interface should be common in kernel.
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Change subject: drivers/intel/dptf: Add support for Battery participant
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
I mean will the data read from EC method?
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Change subject: mb/google/brya: Disable PCH USB2 phy power gating
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
do you need this for brask as well?
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Change subject: drivers/intel/dptf: Add support for Battery participant
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS1:
> Will this duplicate from EC BAT0?
I believe BAT0 of EC0 would be under \_SB.PCI0.LPCB.EC0.BAT0 and this would be under \_SB.DPTF.BAT1, so would be still conflicting ?
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/63315/comment/11255003_26deefdb
PS1, Line 17: DPTF_GENERIC_PARTICIPANT_TYPE_POWER = 0x11,
> nits:put in order
Done
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63315
to look at the new patch set (#2).
Change subject: drivers/intel/dptf: Add support for Battery participant
......................................................................
drivers/intel/dptf: Add support for Battery participant
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)
Add support for BAT1 device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check BAT1 device
Device (BAT1)
{
Name (_HID, "INTC1061") // _HID: Hardware ID
Name (_UID, "BAT1") // _UID: Unique ID
Name (_STR, "Battery Participant") // _STR: Description String
Name (PTYP, 0xC)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516
---
M src/acpi/acpigen_dptf.c
M src/drivers/intel/dptf/Kconfig
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/dptf/dptf.h
M src/include/acpi/acpigen_dptf.h
5 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63315/2
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