coreboot-gerrit April 2022

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Change in coreboot[master]: soc/amd/common/block/spi: Disable SPI Clock Pulldown
by Raul Rangel (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63307 ) Change subject: soc/amd/common/block/spi: Disable SPI Clock Pulldown ...................................................................... Patch Set 1: (2 comments) File src/soc/amd/common/block/include/amdblocks/acpimmio.h: https://review.coreboot.org/c/coreboot/+/63307/comment/2c336bf8_c374f410 PS1, Line 35: 0x90 Does this apply to all the generations? File src/soc/amd/common/block/spi/fch_spi.c: https://review.coreboot.org/c/coreboot/+/63307/comment/ba3b7069_3c696ac7 PS1, Line 133: PM_SPI_CLK_PD_EN Did the default change on sabrina? -- To view, visit https://review.coreboot.org/c/coreboot/+/63307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If62a1f51ac3d68e7896baac3c696c4f73d900f6d Gerrit-Change-Number: 63307 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Apr 2022 22:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superiotool/ite.c: add IT8265E EC registers
by Michał Kopeć (Code Review) 01 Apr '22

01 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63310 ) Change subject: superiotool/ite.c: add IT8265E EC registers ...................................................................... superiotool/ite.c: add IT8265E EC registers Add support for dumping ITE IT8625E Environmental Controller registers. Values as per "IT8625E Preliminary Specification V0.3 (For D Version)". Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M util/superiotool/ite.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63310/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 9b29ceb..31fc496 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1325,6 +1325,43 @@ 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA, NANA,NANA,NANA,EOT}}, {EOT}}}, + {0x8625, "IT8625E", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32, + 0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c, + 0x3d,0x3e,0x3f,0x40,0x41,0x42,0x43,0x44,0x45,0x46, + 0x47,0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58, + 0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62, + 0x63,0x64,0x65,0x66,0x68,0x69,0x6a,0x6b,0x6c,0x6d, + 0x6e,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x78,0x79, + 0x7a,0x7b,0x7c,0x7d,0x7e,0x80,0x81,0x82,0x83,0x84, + 0x85,0x86,0x87,0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e, + 0x8f,0x90,0x91,0x92,0x93,0x94,0x98,0x99,0x9c,0x9d, + 0x9e,0x9f,0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa8, + 0xa9,0xaa,0xab,0xac,0xad,0xae,0xb2,0xb3,0xb4,0xb5, + 0xb6,0xb7,0xb8,0xb9,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0, + 0x44,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x00, + 0x40,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA, + 0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,0x00,0x00,0x7f,0x7f,0x7f,0x40,0x00,0x00,0x90, + 0x00,0x00,0x12,0x60,0x00,0x00,0x00,0x7f,0x7f,0x7f, + 0x00,0x00,0x7f,0x0f,0x7f,0x7f,0x7f,0x00,0x00,0x7f, + 0x0f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,0x7f,0x7f, + 0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + NANA,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,NANA, + 0x00,NANA,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,0x7f, + 0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {0x8716, "IT8716F", { {NOLDN, NULL, {0x00,0x04,0x05,0x06,0x07,0x08,0x09,0x0b,0x0c,0x10, -- To view, visit https://review.coreboot.org/c/coreboot/+/63310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Gerrit-Change-Number: 63310 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/releases: Deprecate Intel Quark SoC
by ron minnich (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Felix Singer, Martin Roth, Paul Menzel, Angel Pons, Michael Niewöhner. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63283 ) Change subject: Documentation/releases: Deprecate Intel Quark SoC ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: This is a single-core part which ran at 400 mhz. The last new one was released 7 years ago as a 32mhz part. This chip was EOL 3 years ago with final shipments july 2022. It was never very good anyway: "Intel Quark SoC X1000 contains a bug #71538[15] that "under specific circumstances" results in a type of crash known as a segfault. The workaround implemented by Intel is to omit LOCK prefixes (not required on single-threaded processors) in the compiled code." You have to wonder how much anyone cared if they did not get LOCK right; LOCK was an original i8086 instruction. In all my discussions with Intel about this chip, I never came away with a feeling they had much enthusiasm for it. As was pointed out elsewhere, "Originally meant to power emerging mass market devices, Intel’s Quark SoCs and microcontrollers have barely become popular among makers of actual products. Therefore, it is not surprising that Intel discontinues the lineup without introducing any direct replacements." You can buy a MUCH better board -- more cores, more HZ, more memory -- with a multicore riscv or arm for $10. Note, too, this is git: nothing is ever really removed. I recently went back to LinuxBIOS v1 to find some old code of mine. -- To view, visit https://review.coreboot.org/c/coreboot/+/63283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e437d363c90c5155d6723a4377dc6052e80ebe7 Gerrit-Change-Number: 63283 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 01 Apr 2022 21:38:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz
by Tim Wawrzynczak (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Eddy Lu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63241 ) Change subject: mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHz ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Gerrit-Change-Number: 63241 Gerrit-PatchSet: 2 Gerrit-Owner: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Reviewer: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <coreboot.test(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 21:26:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [NEEDTEST]soc/amd/non-car: Don't add bootblock cbfs file
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63226 ) Change subject: [NEEDTEST]soc/amd/non-car: Don't add bootblock cbfs file ...................................................................... Patch Set 4: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187 Gerrit-Change-Number: 63226 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Apr 2022 20:38:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apl: Drop cbfs bootblock
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63225 ) Change subject: soc/intel/apl: Drop cbfs bootblock ...................................................................... Patch Set 4: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Gerrit-Change-Number: 63225 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 20:37:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apl: Write to cbfs regions using intermediate targets
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63224 ) Change subject: soc/intel/apl: Write to cbfs regions using intermediate targets ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Gerrit-Change-Number: 63224 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 20:36:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Improve build flow
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56119 ) Change subject: security/intel/cbnt/Makefile.inc: Improve build flow ...................................................................... Patch Set 10: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Gerrit-Change-Number: 56119 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 01 Apr 2022 20:30:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56118 ) Change subject: soc/intel/common/block/fast_spi/Makefile.inc: Improve cosmetics ...................................................................... Patch Set 10: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41bbdabf7b846386651e64f4afb5b7b9fb38e1cb Gerrit-Change-Number: 56118 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 20:30:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/spi: Disable SPI Clock Pulldown
by Karthik Ramasubramanian (Code Review) 01 Apr '22

01 Apr '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63307 ) Change subject: soc/amd/common/block/spi: Disable SPI Clock Pulldown ...................................................................... soc/amd/common/block/spi: Disable SPI Clock Pulldown SPI Clock pulldown is enabled by default. When the bus is idle, this causes the clock signal to be pulled down to 1.3V. Disable the SPI Clock pulldown so that it is parked correctly at idle state. BUG=b:226634752 TEST=Build and boot to OS in Skyrim. Ensure that the SPI clock pulldown is disabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: If62a1f51ac3d68e7896baac3c696c4f73d900f6d --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/spi/fch_spi.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63307/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 2d632f6..6694e80 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -32,6 +32,8 @@ #define SLPTYPE_CONTROL_EN (1 << 5) #define KBRSTEN (1 << 4) #define PM_RST_STATUS 0xc0 +#define PM_SPI_PAD_PUPD 0x90 +#define PM_SPI_CLK_PD_EN (1 << 11) /* * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 5ef900c..a3a721a 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> #include <amdblocks/chip.h> #include <amdblocks/lpc.h> #include <amdblocks/psp_efs.h> @@ -125,4 +126,9 @@ lpc_enable_spi_prefetch(); fch_spi_configure_4dw_burst(); fch_spi_config_modes(); + /* + * SPI Clock Pulldown is enabled by default. Disable SPI Clock Pulldown so that + * the clock signal is parked correctly at idle state. + */ + pm_write32(PM_SPI_PAD_PUPD, pm_read32(PM_SPI_PAD_PUPD) & ~PM_SPI_CLK_PD_EN); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If62a1f51ac3d68e7896baac3c696c4f73d900f6d Gerrit-Change-Number: 63307 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022