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Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
Patch Set 7:
(13 comments)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/62772/comment/1600e492_f58f77b5
PS7, Line 56: ifd2
Why not "mtl" instead? ifdtool seems to know about it.
File src/soc/intel/meteorlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/b79253fb_df72a49b
PS7, Line 85: */
nit: add space before comment end
File src/soc/intel/meteorlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/3031443f_128514a5
PS7, Line 27: MeteorLake
Hmmm, the other entries spell "Meteorlake" with the 'l' in lowercase. Which form is preferred?
File src/soc/intel/meteorlake/include/soc/espi.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/e1309db8_82f4db03
PS7, Line 17: */
nit: Add space before comment end
https://review.coreboot.org/c/coreboot/+/62772/comment/ddc68bae_bba74706
PS7, Line 18: */
nit: Add space before comment end
https://review.coreboot.org/c/coreboot/+/62772/comment/c84c95d7_cf2fe071
PS7, Line 24: #define PCCTL 0xE0 /* PCI Clock Control */
Does this register actually exist? It only seems to exist on platforms that have LPC.
File src/soc/intel/meteorlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/94b80dfd_b6298d82
PS7, Line 51: 4KB
nit: Technically, 4 KiB
https://review.coreboot.org/c/coreboot/+/62772/comment/8a36b854_becb3e82
PS7, Line 73: /*
: #define PID_IOM 0xAA
: #define IOM_BASE_ADDR (IOE_PCR_ABOVE_4G_BASE_ADDR + (PID_IOM << 16))
: */
Why is this commented out?
File src/soc/intel/meteorlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/1253b53b_f3786178
PS7, Line 11: pcidev_path_on_root_debug
Could we please use `pcidev_path_on_root` instead?
https://review.coreboot.org/c/coreboot/+/62772/comment/80fb56c3_2f982a9e
PS7, Line 59: #define PCI_DEV_SLOT_GNA 0x08
: #define PCI_DEVFN_GNA _PCI_DEVFN(GNA, 0)
: #define PCI_DEV_GNA _PCI_DEV(GNA, 0)
nit: Move above `PCI_DEV_SLOT_TCSS` to keep ordering?
https://review.coreboot.org/c/coreboot/+/62772/comment/81fc5dd3_4f792931
PS7, Line 159: #define PCI_DEV_SLOT_PCIE_2 0x6
: #define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0)
: #define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1)
: #define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2)
: #define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0)
: #define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1)
: #define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2)
:
: #define PCI_DEV_SLOT_PCIE_3 0x1
: #define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0)
: #define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0)
I'd prefer to keep the macros ordered as per device/function numbers.
Looking at ADL, I imagine these PCIe RPs are located on the "north" part of the SoC, whereas the PCIe RPs of device 0x1c are located on the "south" part of the SoC.
File src/soc/intel/meteorlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/e88232d7_bca99dc2
PS7, Line 29: #define PID_IOM 0xAA
: #define PID_TC_IOM 0xAA
Is it intentional that these defines have the same value?
File src/soc/intel/meteorlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/f2eb619b_42d588e0
PS7, Line 150: /* Get base address PMC memory mapped registers. */
: uint8_t *pmc_mmio_regs(void);
:
: /* Get base address of TCO I/O registers. */
: uint16_t smbus_tco_regs(void);
:
: /* Set the DISB after DRAM init */
: void pmc_set_disb(void);
:
: /* Clear PMCON status bits */
: void pmc_clear_pmcon_sts(void);
:
: /* STM Support */
: uint16_t get_pmbase(void);
These are unused
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Change subject: amdfwtool: remove duplicates
......................................................................
Patch Set 1:
(1 comment)
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/59581/comment/b488191e_2c56bafe
PS1, Line 205: if (cb_config->use_secureos) {
: fw_type = AMD_FW_PSP_TRUSTLETS;
: subprog = 0;
: } else {
: fw_type = AMD_FW_SKIP;
: }
> Just to be sure, is this correct? The removed duplicate condition always used `AMD_FW_PSP_TRUSTLETS` […]
To be honest there's no documentation so I don't know, need review from AMD. Practically use_secureos is enabled on stoney/picasso/cezanne/sabrina(afaik all platforms with PSP) so it won't make any difference.
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Change subject: intel/common/block: move gpmr api to gpmr driver
......................................................................
Patch Set 9: Code-Review+1
(1 comment)
File src/soc/intel/common/block/gpmr/Kconfig:
https://review.coreboot.org/c/coreboot/+/63170/comment/c5a63f77_2411eeea
PS9, Line 3: depends on SOC_INTEL_COMMON_BLOCK_DMI
The commit message says that the "gpmr api is not DMI specific". I guess this dependency is here because the non-DMI code depends on CB:63198
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Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63293/comment/2f378d56_7507f086
PS3, Line 11: informatrion
> information
Ack
Patchset:
PS2:
> Can we at least add the Problem statement from the TA?
Sure, I will add in other CL where .
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63293/comment/41225d5e_4fad9972
PS4, Line 571: Enable
> I'd use `Disable` instead, given the option's name
Ack
https://review.coreboot.org/c/coreboot/+/63293/comment/06f59cc7_d4f5e5c7
PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
> I feel this is redundant. […]
I will add the comment in other CL.
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Change subject: mb/google/{brya, brask}: Disable PCH USB2 phy power gating
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63294/comment/d23adc5e_1b8bff0f
PS4, Line 9: The patch disables PCH USB2 Phy power gating. This change is required
: to prevent possible display flicker issue.
> Shorter: […]
Ack
https://review.coreboot.org/c/coreboot/+/63294/comment/6073c5fb_57d092ca
PS4, Line 10: to prevent possible display flicker issue
> “possible” means it was never reproduced in practice and is theoretical, or it happens sometimes, an […]
Correct, theoretical possibility and we have noticed the issue from few boards!
File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/63294/comment/c4abefa8_b1dcf808
PS4, Line 25: # Disable PCH USB2 Phy power gating
> I see all the other entries have comments, but in this case the variable names are self-describing, […]
Ack
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Change subject: soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
......................................................................
soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.
Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.
Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com>
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63352/3
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Change subject: soc/intel/ehl/fsp_params.c: Set Intel Speed Step (Eist) from devicetree
......................................................................
soc/intel/ehl/fsp_params.c: Set Intel Speed Step (Eist) from devicetree
This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.
Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.
Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
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---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
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Change subject: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63295/comment/08de9e9e_b41f3b18
PS1, Line 9: Setting the clock source depends on clock request pin for WLAN/SD/SSD device.
: Also turn off the unused (CLKREQ#3) clock sources.
: In skyrim, clock source 0/1/2 are routed for WLAN/SD/SSD device.
> Please wrap lines after 72 characters, do *not* break lines after each sentence, and if you use para […]
Done
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Change subject: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
......................................................................
mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.
BUG=b:227297986
BRANCH=none
TEST=Build
Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
---
M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63295/2
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Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com>
Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
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Gerrit-MessageType: newpatchset