April 2022 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
by build bot (Jenkins) (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Subrata Banik, Reka Norman, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63339 ) Change subject: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Gerrit-Change-Number: 63339 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 08:25:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Add support to update descriptor at runtime
by Reka Norman (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Sam McNally, Kangheui Won, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak. Hello Sam McNally, build bot (Jenkins), Reka Norman, Kangheui Won, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63365 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Add support to update descriptor at runtime ...................................................................... soc/intel/alderlake: Add support to update descriptor at runtime On nereid, we need to update the descriptor based on fw_config (see the following patch), so add support to update the descriptor at runtime. This is a temporary workaround while we find a better solution. This is basically adding back the configure_pmc_descriptor() function removed in CB:63339, just making it generic. BUG=b:226848617 TEST=With the following patch, Type-C and HDMI work on nereid. Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/bootblock/update_descriptor.c M src/soc/intel/alderlake/include/soc/bootblock.h 4 files changed, 93 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Gerrit-Change-Number: 63365 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/nereid: Configure Type-C CSE strap based on fw_config
by Reka Norman (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Sam McNally, Reka Norman, Kangheui Won, Tim Wawrzynczak. Hello Sam McNally, build bot (Jenkins), Reka Norman, Kangheui Won, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63366 to look at the new patch set (#3). Change subject: mb/google/brya/var/nereid: Configure Type-C CSE strap based on fw_config ...................................................................... mb/google/brya/var/nereid: Configure Type-C CSE strap based on fw_config The Type-C Port 2 CSE strap needs to be configured differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the strap at runtime based on fw_config. This is a temporary workaround while we find a better solution. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/bootblock.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/nereid/Makefile.inc M src/mainboard/google/brya/variants/nereid/variant.c 5 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63366/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Gerrit-Change-Number: 63366 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Add support to update CSE descriptor at runtime
by Sridhar Siricilla (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Sam McNally, Reka Norman, Kangheui Won, Rizwan Qureshi, Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63365 ) Change subject: soc/intel/alderlake: Add support to update CSE descriptor at runtime ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63365/comment/d1bed0a0_b917395f PS2, Line 7: CSE Reference to CSE is not required here since CSE and DESC are different regions in the flash. We can drop `CSE` here. Please make this change in all places wherever CSE is referred in this CL. Make sense? -- To view, visit https://review.coreboot.org/c/coreboot/+/63365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Gerrit-Change-Number: 63365 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Apr 2022 08:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Angel Pons (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Raj Astekar. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 ) Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/meteorlake/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/62772/comment/ce72bf56_4f5edba6 PS7, Line 110: #define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2) : #define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3) Do these still exist? -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 7 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 08:02:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: implement ioc driver
by Angel Pons (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Jamie Ryu, Wonkyu Kim, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 ) Change subject: soc/intel/common: implement ioc driver ...................................................................... Patch Set 5: (9 comments) File src/soc/intel/common/block/include/intelblocks/ioc.h: https://review.coreboot.org/c/coreboot/+/63198/comment/455dc1de_7542f64e PS5, Line 12: /* nit: Add space after comment beginning File src/soc/intel/common/block/include/intelblocks/ioc_reg.h: https://review.coreboot.org/c/coreboot/+/63198/comment/21a944aa_e476ce23 PS5, Line 7: A Please use lowercase for hex https://review.coreboot.org/c/coreboot/+/63198/comment/c41ef23e_1f04c80a PS5, Line 8: C Ditto https://review.coreboot.org/c/coreboot/+/63198/comment/cfef4ac2_a913b552 PS5, Line 13: FFE Ditto https://review.coreboot.org/c/coreboot/+/63198/comment/39aa38dc_e6f6669e PS5, Line 14: A7C Ditto https://review.coreboot.org/c/coreboot/+/63198/comment/9124f2cc_a7d10b42 PS5, Line 15: A Ditto File src/soc/intel/common/block/smbus/tco.c: https://review.coreboot.org/c/coreboot/+/63198/comment/58ffa76e_0fb28332 PS5, Line 126: " Remove stray " File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63198/comment/154c9cb2_091a5f75 PS5, Line 31: if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) As per the coding style, this should have braces: https://doc.coreboot.org/contributing/coding_style.html#placing-braces-and-… > This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches: https://review.coreboot.org/c/coreboot/+/63198/comment/59b48d46_7cc26683 PS5, Line 35: /* : * GCS reg of DMI : * : * When set, prevents GCS.BBS from being changed : * GCS.BBS: (Boot BIOS Strap) This field determines the destination : * of accesses to the BIOS memory range. : * Bits Description : * "0b": SPI : * "1b": LPC/eSPI : */ : pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); : : /* : * Set Secure Register Lock (SRL) bit in DMI control register to lock : * DMI configuration. : */ Please indent the comments accordingly as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 07:54:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage
by Angel Pons (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Wonkyu Kim, Ravishankar Sarawadi, Raj Astekar. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63363 ) Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage ...................................................................... Patch Set 3: (20 comments) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/63363/comment/9bc5a86c_b8fead2b PS3, Line 80: config MMCONF_BASE_ADDRESS This was correct, the options were renamed File src/soc/intel/meteorlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63363/comment/fef522dd_d763a1eb PS3, Line 6: subdirs-y += ../../../cpu/x86/lapic See CB:44228 https://review.coreboot.org/c/coreboot/+/63363/comment/7396225e_3efea21f PS3, Line 7: subdirs-y += ../../../cpu/x86/mtrr See CB:44230 https://review.coreboot.org/c/coreboot/+/63363/comment/52de70e1_79fdab82 PS3, Line 8: subdirs-y += ../../../cpu/x86/tsc See CB:57456 File src/soc/intel/meteorlake/chip.h: https://review.coreboot.org/c/coreboot/+/63363/comment/effe332b_ec5362e7 PS3, Line 88: uint8_t SataEnable; Other platforms don't need this, the FSP UPD is programmed as follows: s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); https://review.coreboot.org/c/coreboot/+/63363/comment/2fa32fc7_286657a1 PS3, Line 133: /* Gfx related */ : enum { : IGD_SM_0MB = 0x00, : IGD_SM_32MB = 0x01, : IGD_SM_64MB = 0x02, : IGD_SM_96MB = 0x03, : IGD_SM_128MB = 0x04, : IGD_SM_160MB = 0x05, : IGD_SM_4MB = 0xF0, : IGD_SM_8MB = 0xF1, : IGD_SM_12MB = 0xF2, : IGD_SM_16MB = 0xF3, : IGD_SM_20MB = 0xF4, : IGD_SM_24MB = 0xF5, : IGD_SM_28MB = 0xF6, : IGD_SM_36MB = 0xF8, : IGD_SM_40MB = 0xF9, : IGD_SM_44MB = 0xFA, : IGD_SM_48MB = 0xFB, : IGD_SM_52MB = 0xFC, : IGD_SM_56MB = 0xFD, : IGD_SM_60MB = 0xFE, : } IgdDvmt50PreAlloc; : uint8_t SkipExtGfxScan; I'm pretty sure this won't be used https://review.coreboot.org/c/coreboot/+/63363/comment/b081a3f2_6332b4bd PS3, Line 160: uint8_t HeciEnabled; This is no longer used, see https://review.coreboot.org/q/topic:retire_hecienabled https://review.coreboot.org/c/coreboot/+/63363/comment/63100857_5ceb830d PS3, Line 167: uint8_t PmTimerDisabled; This doesn't seem to be used https://review.coreboot.org/c/coreboot/+/63363/comment/6f894473_1c846bbb PS3, Line 219: ADL Hmmmmmmmmm... https://review.coreboot.org/c/coreboot/+/63363/comment/194ab8cf_6d8f7b57 PS3, Line 293: IsaSerialUartBase This shouldn't be a devicetree option, the correct value can be determined from Kconfig options. ADL always uses 3F8 anyway. File src/soc/intel/meteorlake/espi.c: https://review.coreboot.org/c/coreboot/+/63363/comment/9dc9d337_d03033f9 PS3, Line 3: nit: double empty line File src/soc/intel/meteorlake/include/soc/msr.h: https://review.coreboot.org/c/coreboot/+/63363/comment/06d98ce6_f0b83786 PS3, Line 8: #define MSR_VR_MISC_CONFIG2 0x636 Does this MSR actually exist? Looks like it has been copy-pasted from Haswell/Broadwell code... File src/soc/intel/meteorlake/include/soc/p2sb.h: https://review.coreboot.org/c/coreboot/+/63363/comment/efae6a96_4d0f794a PS3, Line 3: /* : * This file is created based on Intel Alder Lake Processor PCH Datasheet : * Document number: 621483 : * Chapter number: 3 : */ : : #ifndef _SOC_ALDERLAKE_P2SB_H_ : #define _SOC_ALDERLAKE_P2SB_H_ Hmmmmmmmmm... File src/soc/intel/meteorlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/63363/comment/df0b1ce9_f323a9f3 PS3, Line 10: mainboard_update_premem_soc_chip_config How is this supposed to work? The devicetree is read-only in pre-mem stages. File src/soc/intel/meteorlake/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/63363/comment/3feaf790_9a9e6c26 PS3, Line 3: nit: double blank line https://review.coreboot.org/c/coreboot/+/63363/comment/c85eb49b_1eda2cd3 PS3, Line 12: #define DMIBAR 0x68 I thought MTL doesn't have DMI? File src/soc/intel/meteorlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/63363/comment/d8be46cd_7687abcb PS3, Line 31: trailing whitespace https://review.coreboot.org/c/coreboot/+/63363/comment/c6d254a6_48749d7a PS3, Line 73: m_cfg->CpuPcieRpEnableMask = 0; Always 0? https://review.coreboot.org/c/coreboot/+/63363/comment/9631e134_feb87539 PS3, Line 229: trailing whitespace File src/soc/intel/meteorlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/63363/comment/2c8cc77d_ebdedb71 PS3, Line 129: /* FIXME: Reset Heci interface : * This is a W/A added until heci_reset is included to heci_init : */ : heci_reset(); Is this still needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/63363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14 Gerrit-Change-Number: 63363 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 07:52:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: amdfwtool: Add a flag to record the second gen instead of romsig
by Bao Zheng (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63344 ) Change subject: amdfwtool: Add a flag to record the second gen instead of romsig ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > should cb_config.second_gen also be used to populate amd_romsig->efs_gen. […] done. -- To view, visit https://review.coreboot.org/c/coreboot/+/63344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Gerrit-Change-Number: 63344 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Apr 2022 07:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: amdfwtool: Add a flag to record the second gen instead of romsig
by Bao Zheng (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Bao Zheng, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63344 to look at the new patch set (#3). Change subject: amdfwtool: Add a flag to record the second gen instead of romsig ...................................................................... amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 38 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/63344/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Gerrit-Change-Number: 63344 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Add support to update CSE descriptor at runtime
by Reka Norman (Code Review) April 5, 2022

April 5, 2022

Attention is currently required from: Reka Norman, Tim Wawrzynczak. Hello build bot (Jenkins), Reka Norman, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63365 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Add support to update CSE descriptor at runtime ...................................................................... soc/intel/alderlake: Add support to update CSE descriptor at runtime On nereid, we need to update the CSE descriptor based on fw_config (see the following patch), so add support to update the descriptor at runtime. This is a temporary workaround while we find a better solution. This is basically adding back the configure_pmc_descriptor() function removed in CB:63339, just making it generic. BUG=b:226848617 TEST=With the following patch, Type-C and HDMI work on nereid. Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/bootblock/cse_descriptor.c M src/soc/intel/alderlake/include/soc/bootblock.h 4 files changed, 93 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Gerrit-Change-Number: 63365 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0