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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 )
Change subject: soc/intel/common: implement ioc driver
......................................................................
Patch Set 5:
(9 comments)
File src/soc/intel/common/block/include/intelblocks/ioc.h:
https://review.coreboot.org/c/coreboot/+/63198/comment/455dc1de_7542f64e
PS5, Line 12: /*
nit: Add space after comment beginning
File src/soc/intel/common/block/include/intelblocks/ioc_reg.h:
https://review.coreboot.org/c/coreboot/+/63198/comment/21a944aa_e476ce23
PS5, Line 7: A
Please use lowercase for hex
https://review.coreboot.org/c/coreboot/+/63198/comment/c41ef23e_1f04c80a
PS5, Line 8: C
Ditto
https://review.coreboot.org/c/coreboot/+/63198/comment/cfef4ac2_a913b552
PS5, Line 13: FFE
Ditto
https://review.coreboot.org/c/coreboot/+/63198/comment/39aa38dc_e6f6669e
PS5, Line 14: A7C
Ditto
https://review.coreboot.org/c/coreboot/+/63198/comment/9124f2cc_a7d10b42
PS5, Line 15: A
Ditto
File src/soc/intel/common/block/smbus/tco.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/58ffa76e_0fb28332
PS5, Line 126: "
Remove stray "
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/154c9cb2_091a5f75
PS5, Line 31: if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC))
As per the coding style, this should have braces: https://doc.coreboot.org/contributing/coding_style.html#placing-braces-and-…
> This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches:
https://review.coreboot.org/c/coreboot/+/63198/comment/59b48d46_7cc26683
PS5, Line 35: /*
: * GCS reg of DMI
: *
: * When set, prevents GCS.BBS from being changed
: * GCS.BBS: (Boot BIOS Strap) This field determines the destination
: * of accesses to the BIOS memory range.
: * Bits Description
: * "0b": SPI
: * "1b": LPC/eSPI
: */
: pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
:
: /*
: * Set Secure Register Lock (SRL) bit in DMI control register to lock
: * DMI configuration.
: */
Please indent the comments accordingly as well.
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Change subject: amdfwtool: Add a flag to record the second gen instead of romsig
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> should cb_config.second_gen also be used to populate amd_romsig->efs_gen. […]
done.
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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63344
to look at the new patch set (#3).
Change subject: amdfwtool: Add a flag to record the second gen instead of romsig
......................................................................
amdfwtool: Add a flag to record the second gen instead of romsig
This is for future feature combo, which gets the soc id from fw.cfg in
a loop instead of the command line, and the romsig is not set until
fw.cfg is processed.
Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 38 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/63344/3
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Hello build bot (Jenkins), Reka Norman, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63365
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Add support to update CSE descriptor at runtime
......................................................................
soc/intel/alderlake: Add support to update CSE descriptor at runtime
On nereid, we need to update the CSE descriptor based on fw_config (see
the following patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.
This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic.
BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.
Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/bootblock/cse_descriptor.c
M src/soc/intel/alderlake/include/soc/bootblock.h
4 files changed, 93 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63365 )
Change subject: soc/intel/alderlake: Add support to update CSE descriptor at runtime
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/alderlake/bootblock/cse_descriptor.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145364):
https://review.coreboot.org/c/coreboot/+/63365/comment/6294f711_b4b87411
PS1, Line 40: void configure_cse_descriptor(size_t byte, uint8_t desired_value) {
open brace '{' following function definitions go on the next line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145364):
https://review.coreboot.org/c/coreboot/+/63365/comment/bc7c9d95_f0abf10d
PS1, Line 58: printk(BIOS_DEBUG, "Current value of Descriptor byte 0x%lx: 0x%x\n", byte, si_desc_buf[byte]);
line over 96 characters
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Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63365 )
Change subject: soc/intel/alderlake: Add support to update CSE descriptor at runtime
......................................................................
soc/intel/alderlake: Add support to update CSE descriptor at runtime
On nereid, we need to update the CSE descriptor based on fw_config (see
the following patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.
This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic.
BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.
Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/bootblock/cse_descriptor.c
M src/soc/intel/alderlake/include/soc/bootblock.h
4 files changed, 91 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63365/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index eed157a..03b8160 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -112,6 +112,13 @@
select UDK_202005_BINDING
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+config ALDERLAKE_CONFIGURE_CSE_DESCRIPTOR
+ bool
+ help
+ Select this if the CSE descriptor needs to be updated at runtime. This
+ can only be done if the descriptor region is writable, and should only
+ be used as a temporary workaround.
+
config ALDERLAKE_CAR_ENHANCED_NEM
bool
default y if !INTEL_CAR_NEM
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index d2c48b7..bd0bba6 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -16,6 +16,7 @@
bootblock-y += espi.c
bootblock-y += gpio.c
bootblock-y += p2sb.c
+bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_CSE_DESCRIPTOR) += bootblock/cse_descriptor.c
romstage-y += espi.c
romstage-y += gpio.c
diff --git a/src/soc/intel/alderlake/bootblock/cse_descriptor.c b/src/soc/intel/alderlake/bootblock/cse_descriptor.c
new file mode 100644
index 0000000..8b6550d
--- /dev/null
+++ b/src/soc/intel/alderlake/bootblock/cse_descriptor.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <arch/cpu.h>
+#include <arch/mmio.h>
+#include <cf9_reset.h>
+#include <commonlib/region.h>
+#include <console/console.h>
+#include <cpu/intel/cpu_ids.h>
+#include <fmap.h>
+#include <intelblocks/pmclib.h>
+#include <soc/bootblock.h>
+#include <types.h>
+
+/* Flash Master 1 : HOST/BIOS */
+#define FLMSTR1 0x80
+
+/* Flash signature Offset */
+#define FLASH_SIGN_OFFSET 0x10
+#define FLMSTR_WR_SHIFT_V2 20
+#define FLASH_VAL_SIGN 0xFF0A55A
+
+/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */
+static int is_descriptor_writeable(uint8_t *desc)
+{
+ /* Check flash has valid signature */
+ if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) {
+ printk(BIOS_DEBUG, "Flash Descriptor is not valid\n");
+ return 0;
+ }
+
+ /* Check host has write access to the Descriptor Region */
+ if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) {
+ printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+void configure_cse_descriptor(size_t byte, uint8_t desired_value) {
+ uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ];
+ struct region_device desc_rdev;
+
+ if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) {
+ printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", CONFIG_SI_DESC_REGION);
+ return;
+ }
+
+ if (rdev_readat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) !=
+ CONFIG_SI_DESC_REGION_SZ) {
+ printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n");
+ return;
+ }
+
+ if (!is_descriptor_writeable(si_desc_buf))
+ return;
+
+ printk(BIOS_DEBUG, "Current value of Descriptor byte 0x%lx: 0x%x\n", byte, si_desc_buf[byte]);
+ if (si_desc_buf[byte] == desired_value) {
+ printk(BIOS_DEBUG, "Update of Descriptor is not required!\n");
+ return;
+ }
+
+ si_desc_buf[byte] = desired_value;
+
+ if (rdev_eraseat(&desc_rdev, 0, CONFIG_SI_DESC_REGION_SZ) != CONFIG_SI_DESC_REGION_SZ) {
+ printk(BIOS_ERR, "Failed to erase Descriptor Region area\n");
+ return;
+ }
+
+ if (rdev_writeat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ)
+ != CONFIG_SI_DESC_REGION_SZ) {
+ printk(BIOS_ERR, "Failed to update Descriptor Region\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "Update of Descriptor successful, trigger GLOBAL RESET\n");
+
+ pmc_global_reset_enable(true);
+ do_full_reset();
+ die("Failed to trigger GLOBAL RESET\n");
+}
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index e989bdd..54467fa 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -17,6 +17,6 @@
void pch_early_iorange_init(void);
void report_platform_info(void);
-void configure_pmc_descriptor(void);
+void configure_cse_descriptor(size_t byte, uint8_t desired_value);
#endif
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Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
......................................................................
Patch Set 7:
(13 comments)
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/62772/comment/1600e492_f58f77b5
PS7, Line 56: ifd2
Why not "mtl" instead? ifdtool seems to know about it.
File src/soc/intel/meteorlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/b79253fb_df72a49b
PS7, Line 85: */
nit: add space before comment end
File src/soc/intel/meteorlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/3031443f_128514a5
PS7, Line 27: MeteorLake
Hmmm, the other entries spell "Meteorlake" with the 'l' in lowercase. Which form is preferred?
File src/soc/intel/meteorlake/include/soc/espi.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/e1309db8_82f4db03
PS7, Line 17: */
nit: Add space before comment end
https://review.coreboot.org/c/coreboot/+/62772/comment/ddc68bae_bba74706
PS7, Line 18: */
nit: Add space before comment end
https://review.coreboot.org/c/coreboot/+/62772/comment/c84c95d7_cf2fe071
PS7, Line 24: #define PCCTL 0xE0 /* PCI Clock Control */
Does this register actually exist? It only seems to exist on platforms that have LPC.
File src/soc/intel/meteorlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/94b80dfd_b6298d82
PS7, Line 51: 4KB
nit: Technically, 4 KiB
https://review.coreboot.org/c/coreboot/+/62772/comment/8a36b854_becb3e82
PS7, Line 73: /*
: #define PID_IOM 0xAA
: #define IOM_BASE_ADDR (IOE_PCR_ABOVE_4G_BASE_ADDR + (PID_IOM << 16))
: */
Why is this commented out?
File src/soc/intel/meteorlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/1253b53b_f3786178
PS7, Line 11: pcidev_path_on_root_debug
Could we please use `pcidev_path_on_root` instead?
https://review.coreboot.org/c/coreboot/+/62772/comment/80fb56c3_2f982a9e
PS7, Line 59: #define PCI_DEV_SLOT_GNA 0x08
: #define PCI_DEVFN_GNA _PCI_DEVFN(GNA, 0)
: #define PCI_DEV_GNA _PCI_DEV(GNA, 0)
nit: Move above `PCI_DEV_SLOT_TCSS` to keep ordering?
https://review.coreboot.org/c/coreboot/+/62772/comment/81fc5dd3_4f792931
PS7, Line 159: #define PCI_DEV_SLOT_PCIE_2 0x6
: #define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0)
: #define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1)
: #define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2)
: #define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0)
: #define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1)
: #define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2)
:
: #define PCI_DEV_SLOT_PCIE_3 0x1
: #define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0)
: #define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0)
I'd prefer to keep the macros ordered as per device/function numbers.
Looking at ADL, I imagine these PCIe RPs are located on the "north" part of the SoC, whereas the PCIe RPs of device 0x1c are located on the "south" part of the SoC.
File src/soc/intel/meteorlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/e88232d7_bca99dc2
PS7, Line 29: #define PID_IOM 0xAA
: #define PID_TC_IOM 0xAA
Is it intentional that these defines have the same value?
File src/soc/intel/meteorlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/62772/comment/f2eb619b_42d588e0
PS7, Line 150: /* Get base address PMC memory mapped registers. */
: uint8_t *pmc_mmio_regs(void);
:
: /* Get base address of TCO I/O registers. */
: uint16_t smbus_tco_regs(void);
:
: /* Set the DISB after DRAM init */
: void pmc_set_disb(void);
:
: /* Clear PMCON status bits */
: void pmc_clear_pmcon_sts(void);
:
: /* STM Support */
: uint16_t get_pmbase(void);
These are unused
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