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Change in coreboot[master]: coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t
by Jianjun Wang (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Jakub Czapiga. Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63494 ) Change subject: coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t ...................................................................... coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t Convert 'struct lb_uint64' to 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/bootmem.c M src/lib/coreboot_table.c M tests/lib/bootmem-test.c M tests/lib/coreboot_table-test.c M util/cbmem/cbmem.c M util/nvramtool/coreboot_tables.h M util/nvramtool/lbtable.c 8 files changed, 27 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63494/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 01b12f3..4b3a1f8 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -94,38 +94,7 @@ LB_TAG_OPTION_CHECKSUM = 0x00cc, }; -/* Since coreboot is usually compiled 32bit, gcc will align 64bit - * types to 32bit boundaries. If the coreboot table is dumped on a - * 64bit system, a uint64_t would be aligned to 64bit boundaries, - * breaking the table format. - * - * lb_uint64 will keep 64bit coreboot table values aligned to 32bit - * to ensure compatibility. They can be accessed with the two functions - * below: unpack_lb64() and pack_lb64() - * - * See also: util/lbtdump/lbtdump.c - */ - -struct lb_uint64 { - uint32_t lo; - uint32_t hi; -}; - -static inline uint64_t unpack_lb64(struct lb_uint64 value) -{ - uint64_t result; - result = value.hi; - result = (result << 32) + value.lo; - return result; -} - -static inline struct lb_uint64 pack_lb64(uint64_t value) -{ - struct lb_uint64 result; - result.lo = (value >> 0) & 0xffffffff; - result.hi = (value >> 32) & 0xffffffff; - return result; -} +typedef __aligned(4) uint64_t lb_uint64_t; struct lb_header { uint8_t signature[4]; /* LBIO */ @@ -148,8 +117,8 @@ }; struct lb_memory_range { - struct lb_uint64 start; - struct lb_uint64 size; + lb_uint64_t start; + lb_uint64_t size; uint32_t type; #define LB_MEM_RAM 1 /* Memory anyone can use */ #define LB_MEM_RESERVED 2 /* Don't use this memory region */ @@ -461,7 +430,7 @@ uint32_t tag; uint32_t size; - struct lb_uint64 fw_config; + lb_uint64_t fw_config; uint32_t board_id; uint32_t ram_code; uint32_t sku_id; @@ -583,7 +552,7 @@ struct lb_acpi_rsdp { uint32_t tag; uint32_t size; - struct lb_uint64 rsdp_pointer; /* Address of the ACPI RSDP */ + lb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ }; #endif diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index e9d4287..d4462d8 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -110,8 +110,8 @@ bootmem_dump_ranges(); memranges_each_entry(r, &bootmem_os) { - lb_r->start = pack_lb64(range_entry_base(r)); - lb_r->size = pack_lb64(range_entry_size(r)); + lb_r->start = range_entry_base(r); + lb_r->size = range_entry_size(r); lb_r->type = bootmem_to_lb_tag(range_entry_tag(r)); lb_r++; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3ceab37..c29d308 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -313,7 +313,7 @@ config->board_id = board_id(); config->ram_code = ram_code(); config->sku_id = sku_id(); - config->fw_config = pack_lb64(fw_config); + config->fw_config = fw_config; if (config->board_id != UNDEFINED_STRAPPING_ID) printk(BIOS_INFO, "Board ID: %d\n", config->board_id); @@ -428,7 +428,7 @@ acpi_rsdp = (struct lb_acpi_rsdp *)rec; acpi_rsdp->tag = LB_TAG_ACPI_RSDP; acpi_rsdp->size = sizeof(*acpi_rsdp); - acpi_rsdp->rsdp_pointer = pack_lb64(get_coreboot_rsdp()); + acpi_rsdp->rsdp_pointer = get_coreboot_rsdp(); } size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) diff --git a/tests/lib/bootmem-test.c b/tests/lib/bootmem-test.c index ddd62ae..7bdbf0d 100644 --- a/tests/lib/bootmem-test.c +++ b/tests/lib/bootmem-test.c @@ -177,8 +177,8 @@ required_unused_space_size); for (i = 0; i < lb_mem->size / sizeof(struct lb_memory_range); i++) { - assert_int_equal(unpack_lb64(lb_mem->map[i].start), os_ranges[i].start); - assert_int_equal(unpack_lb64(lb_mem->map[i].size), os_ranges[i].size); + assert_int_equal(lb_mem->map[i].start, os_ranges[i].start); + assert_int_equal(lb_mem->map[i].size, os_ranges[i].size); assert_int_equal(lb_mem->map[i].type, bootmem_to_lb_tag(os_ranges[i].type)); } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index a50dd15..2bf1f61 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -229,8 +229,8 @@ /* Insert entries for testing */ for (i = 0; i < ARRAY_SIZE(mock_bootmem_ranges); ++i) { struct resource *res = &mock_bootmem_ranges[i]; - lb_r->start = pack_lb64(res->base); - lb_r->size = pack_lb64(res->size); + lb_r->start = res->base; + lb_r->size = res->size; lb_r->type = res->flags; lb_r++; mem->size += sizeof(struct lb_memory_range); @@ -362,18 +362,18 @@ const struct lb_memory *memory = (struct lb_memory *)record; const struct lb_memory_range *range; const struct resource *res; - struct lb_uint64 value; + lb_uint64_t value; for (int i = 0; i < ARRAY_SIZE(mock_bootmem_ranges); ++i) { res = &mock_bootmem_ranges[i]; range = &memory->map[i]; - value = pack_lb64(res->base); + value = res->base; assert_memory_equal(&value, &range->start, - sizeof(struct lb_uint64)); - value = pack_lb64(res->size); + sizeof(lb_uint64_t)); + value = res->size; assert_memory_equal(&value, &range->size, - sizeof(struct lb_uint64)); + sizeof(lb_uint64_t)); assert_int_equal(range->type, res->flags); } break; @@ -475,9 +475,9 @@ const struct lb_board_config *board_config = (struct lb_board_config *)record; - const struct lb_uint64 expected_fw_version = pack_lb64(fw_config_get()); + const lb_uint64_t expected_fw_version = fw_config_get(); assert_memory_equal(&expected_fw_version, &board_config->fw_config, - sizeof(struct lb_uint64)); + sizeof(lb_uint64_t)); assert_int_equal(board_id(), board_config->board_id); assert_int_equal(ram_code(), board_config->ram_code); assert_int_equal(sku_id(), board_config->sku_id); @@ -486,7 +486,7 @@ assert_int_equal(sizeof(struct lb_acpi_rsdp), record->size); const struct lb_acpi_rsdp *acpi_rsdp = (struct lb_acpi_rsdp *)record; - assert_int_equal(ebda_base, unpack_lb64(acpi_rsdp->rsdp_pointer)); + assert_int_equal(ebda_base, acpi_rsdp->rsdp_pointer); break; default: fail_msg("Unexpected tag found in record. Tag ID: 0x%x", record->tag); diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 0fd69d6..c9b46a8 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -927,7 +927,7 @@ return; } - hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); + hexdump(cbmem.start, cbmem.size); } static void rawdump(uint64_t base, uint64_t size) diff --git a/util/nvramtool/coreboot_tables.h b/util/nvramtool/coreboot_tables.h index 1417c19..aa0ee97 100644 --- a/util/nvramtool/coreboot_tables.h +++ b/util/nvramtool/coreboot_tables.h @@ -40,38 +40,7 @@ * table entries and be backwards compatible, but it is not required. */ -/* Since coreboot is usually compiled 32bit, gcc will align 64bit - * types to 32bit boundaries. If the coreboot table is dumped on a - * 64bit system, a uint64_t would be aligned to 64bit boundaries, - * breaking the table format. - * - * lb_uint64 will keep 64bit coreboot table values aligned to 32bit - * to ensure compatibility. They can be accessed with the two functions - * below: unpack_lb64() and pack_lb64() - * - * See also: util/lbtdump/lbtdump.c - */ - -struct lb_uint64 { - uint32_t lo; - uint32_t hi; -}; - -static inline uint64_t unpack_lb64(struct lb_uint64 value) -{ - uint64_t result; - result = value.hi; - result = (result << 32) + value.lo; - return result; -} - -static inline struct lb_uint64 pack_lb64(uint64_t value) -{ - struct lb_uint64 result; - result.lo = (value >> 0) & 0xffffffff; - result.hi = (value >> 32) & 0xffffffff; - return result; -} +typedef __aligned(4) uint64_t lb_uint64_t; struct lb_header { union { @@ -101,8 +70,8 @@ #define LB_TAG_MEMORY 0x0001 struct lb_memory_range { - struct lb_uint64 start; - struct lb_uint64 size; + lb_uint64_t start; + lb_uint64_t size; uint32_t type; #define LB_MEM_RAM 1 /* Memory anyone can use */ #define LB_MEM_RESERVED 2 /* Don't use this memory region */ diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c index fd6c9ec..6993cc0 100644 --- a/util/nvramtool/lbtable.c +++ b/util/nvramtool/lbtable.c @@ -632,8 +632,8 @@ break; } - size = unpack_lb64(ranges[i].size); - start = unpack_lb64(ranges[i].start); + size = ranges[i].size; + start = ranges[i].start; end = start + size - 1; printf("%s memory:\n" " from physical addresses 0x%016" PRIx64 -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Jianjun Wang (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63252 to look at the new patch set (#10). Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... soc/mediatek: Fill coreboot table with PCIe info In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 --- M src/soc/mediatek/common/pcie.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63252/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63251 to look at the new patch set (#9). Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... coreboot tables: Add PCIe info to coreboot table Add 'pcie_fill_lb' and 'lb_add_pcie' functions to pass PCIe information from coreboot to libpayload. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller, configuration space and address translation unit for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63251/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63493 ) Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... soc/intel/alderlake: add chipset devicetree for ADL-S Add chipset devicetree for AlderLake-S platform. Based on Intel docs #619015 and #619362. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig A src/soc/intel/alderlake/chipset_pch_s.cb 2 files changed, 130 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63493/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2eeae42..bdd7397 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -166,6 +166,7 @@ config CHIPSET_DEVICETREE string + default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S default "soc/intel/alderlake/chipset.cb" config EXT_BIOS_WIN_BASE diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb new file mode 100644 index 0000000..c95609e --- /dev/null +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -0,0 +1,129 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on end + + device domain 0 on + device gpio 0 alias pch_gpio on end + device pci 00.0 alias system_agent on end + device pci 01.0 alias pcie5_0 off end + device pci 01.1 alias pcie5_1 off end + device pci 02.0 alias igpu off end + device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end + device pci 06.0 alias pcie4_0 off end + device pci 06.2 alias pcie4_1 off end + device pci 08.0 alias gna off end + device pci 09.0 alias north_tracehub off end + device pci 0a.0 alias crashlog on end + device pci 0e.0 alias vmd off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + end + end + end + device pci 14.1 alias xdci off end + device pci 14.2 alias shared_sram off end + device pci 14.3 alias cnvi_wifi off end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 on end + device pci 16.1 alias heci2 off end + device pci 16.2 alias ide_r off end + device pci 16.3 alias kt off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1a.0 alias pcie_rp25 off end + device pci 1a.1 alias pcie_rp26 off end + device pci 1a.2 alias pcie_rp27 off end + device pci 1a.3 alias pcie_rp28 off end + device pci 1b.0 alias pcie_rp17 off end + device pci 1b.1 alias pcie_rp18 off end + device pci 1b.2 alias pcie_rp19 off end + device pci 1b.3 alias pcie_rp20 off end + device pci 1b.4 alias pcie_rp21 off end + device pci 1b.5 alias pcie_rp22 off end + device pci 1b.6 alias pcie_rp23 off end + device pci 1b.7 alias pcie_rp24 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1d.4 alias pcie_rp13 off end + device pci 1d.5 alias pcie_rp14 off end + device pci 1d.6 alias pcie_rp15 off end + device pci 1d.7 alias pcie_rp16 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias south_tracehub off end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Balaji Manigandan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Jakub Czapiga, Selma Bensaid, Tim Wawrzynczak. Balaji Manigandan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63240/comment/47ae3183_e467458e PS3, Line 9: #3461454 > Wait a minute. CONFIG_LP_VBOOT_LIB=y should be set by default. […] Does it mean CONFIG_LP_CHROMEOS=y has to be set in depthcharge board/<BOARD>/defconfig ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 3 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 09:29:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
by Robert Chen (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Robert Chen. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63112 ) Change subject: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/63112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Gerrit-Change-Number: 63112 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 09:12:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrrlib: Use `need restore mtrr()` from set var mtrr function
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63492 ) Change subject: cpu/x86/mtrrlib: Use `need_restore_mtrr()` from set_var_mtrr function ...................................................................... cpu/x86/mtrrlib: Use `need_restore_mtrr()` from set_var_mtrr function `fast_spi_cache_bios_region()` is calling `set_var_mtrr()` to set temporary MTRRs with commit def18c406 (soc/intel/common/block/fast_spi: Refactor ROM caching implementation). Hence, this patch ensures the `put_back_original_solution` variable is also getting set by `need_restore_mtrr()` while calling from the `set_var_mtrr()`. Later `remove_temp_solution()` discard any temporary MTRRs prior to boot to payload. Ensure `set_var_mtrr()` being called during ramstage only sets the `put_back_original_solution` variable. BUG=b:225766934 TEST=Able to build and boot google/brya to verify that `remove_temp_solution()` is able to discard ROM caching temporary MTRRs before booting to payload. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 --- M src/cpu/x86/mtrr/mtrrlib.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63492/1 diff --git a/src/cpu/x86/mtrr/mtrrlib.c b/src/cpu/x86/mtrr/mtrrlib.c index 71921de..ca8a20d 100644 --- a/src/cpu/x86/mtrr/mtrrlib.c +++ b/src/cpu/x86/mtrr/mtrrlib.c @@ -48,6 +48,10 @@ maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); + + /* Need to restore mtrr later using remove_temp_solution. */ + if (ENV_RAMSTAGE) + need_restore_mtrr(); } void clear_all_var_mtrr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/63492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 Gerrit-Change-Number: 63492 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63491 ) Change subject: cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution ...................................................................... cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution This patch calls into need_restore_mtrr() from the mtrr_use_temp_range function to set `put_back_original_solution` to discard any temporary MTRR range prior to boot to payload. BUG=b:225766934 TEST=Able to build and boot google/brya to verify that `remove_temp_solution()` is able to discard any temporary MTRR range before booting to payload. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I2e00ec593847e1eb173d5ac77b15b50342860f89 --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63491/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index e1bdf45..288f06d 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -908,7 +908,7 @@ (long long)begin, (long long)begin + size, (long long)size, type); else - put_back_original_solution = true; + need_restore_mtrr(); memranges_teardown(&addr_space); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e00ec593847e1eb173d5ac77b15b50342860f89 Gerrit-Change-Number: 63491 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86: Add function to set `put_back_original_solution` variable
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik. Subrata Banik has uploaded a new patch set (#2) to the change originally created by Kane Chen. ( https://review.coreboot.org/c/coreboot/+/63485 ) Change subject: cpu/x86: Add function to set `put_back_original_solution` variable ...................................................................... cpu/x86: Add function to set `put_back_original_solution` variable `put_back_original_solution` variable in mtrr.c is static, but there is a need to set put_back_original_solution outside of mtrr.c in order to let `remove_temp_solution` to drop any temporary MTRRs being set outside `mtrr_use_temp_range()`, for example: `set_var_mtrr()` function is used to set MTRRs for the ROM caching. BUG=b:225766934 TEST=Able to build and boot google/redrix. Change-Id: Ic6b5683b2aa7398a5e141f710394ab772e9775e7 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/cpu/x86/mtrr/mtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63485/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b5683b2aa7398a5e141f710394ab772e9775e7 Gerrit-Change-Number: 63485 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/{brya, brask}: Disable PCH USB2 phy power gating
by Angel Pons (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sridhar Siricilla. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/{brya, brask}: Disable PCH USB2 phy power gating ...................................................................... Patch Set 5: Code-Review+1 (3 comments) File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/63294/comment/b5d28725_d8e0b82d PS5, Line 25: the nit: Remove `the` https://review.coreboot.org/c/coreboot/+/63294/comment/ab174eb3_9fb0b2f2 PS5, Line 25: t typo: Remove `t` File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb: https://review.coreboot.org/c/coreboot/+/63294/comment/a915a4fd_ce4dd87d PS5, Line 25: # As per Intel Advistory doc#723158, the change is required to prevent the possible Same comments as on Brask -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 08:14:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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