coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/63293/comment/d219d82b_f4a510af PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. > I'd prefer if you could mention doc#723158 here as well. Hmm, the CL just facilitates to modify PmcUsb2PhySusPgEnable UPD. In general, the UPD can be modified for any other reason if required. It is better the motivation details be part of CL which actually enables the UPD. Agreed? -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:44:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Arthur Heymans (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > > > ah yes, thanks for capturing this. > > > > i miss this. > > > > it only restores BSP MTRR. > > > > > > @Arthur, can you please comment reg CB:63498 > > > > With TXT APs are shut down along the way and not started up again. I know it's a different problem that also needs a solution, but that approach would break it. > > oops I was not aware of that. > > > > > What do you think of my suggestion to add a nop call on APs, to be sure they finished setting up MTRRs and don't override that temp one. Then the temp MTRR is only set on the BSP? > > this would work bt isn't MTRR is shared between logical processors belongs to a core. Is it so bad that one AP also has the temp MTRR? when the BSP removes that temp MTRR that would also be resolved. > > > I generally like to avoid keeping track of the state of APs. > > yeah, that would be complicated. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > > ah yes, thanks for capturing this. > > > i miss this. > > > it only restores BSP MTRR. > > > > @Arthur, can you please comment reg CB:63498 > > With TXT APs are shut down along the way and not started up again. I know it's a different problem that also needs a solution, but that approach would break it. oops I was not aware of that. > > What do you think of my suggestion to add a nop call on APs, to be sure they finished setting up MTRRs and don't override that temp one. Then the temp MTRR is only set on the BSP? this would work bt isn't MTRR is shared between logical processors belongs to a core. > I generally like to avoid keeping track of the state of APs. yeah, that would be complicated. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:37:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Arthur Heymans (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > ah yes, thanks for capturing this. > > i miss this. > > it only restores BSP MTRR. > > @Arthur, can you please comment reg CB:63498 With TXT APs are shut down along the way and not started up again. I know it's a different problem that also needs a solution, but that approach would break it. What do you think of my suggestion to add a nop call on APs, to be sure they finished setting up MTRRs and don't override that temp one. Then the temp MTRR is only set on the BSP? I generally like to avoid keeping track of the state of APs. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Amanda Hwang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63496 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11c5ef9583fbc623adf239db60327a7a4926995 Gerrit-Change-Number: 63496 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63495 to look at the new patch set (#2). Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 Based on the latest schematic, change MAX98360 AMP interface from I2S2 to I2S1 due to Intel BT offload concern. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 --- M src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63495/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Amanda Hwang has restored this change. ( https://review.coreboot.org/c/coreboot/+/63495 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

1 0

Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

1 0

Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63456 ) Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Secondly, the FSP for ADL-S IOT which is already public indicates v2.3 compliance in the header: https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/ADL_IOT/Fsp.fd hexdump -C Fsp.fd: 00000000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| 00000010 78 e5 8c 8c 3d 8a 1c 4f 99 35 89 61 85 c3 2d d3 |x...=..O.5.a..-.| 00000020 00 f0 06 00 00 00 00 00 5f 46 56 48 ff fe 04 00 |........_FVH....| 00000030 48 00 fa f5 60 00 00 02 6f 00 00 00 00 10 00 00 |H...`...o.......| 00000040 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ff ff |................| 00000050 ff ff ff ff ff ff ff ff f4 aa f0 00 2c 00 00 f8 |............,...| 00000060 fe 27 5c 1b 1c f0 bc 4f ae ae 34 1b 2e 99 2a 17 |.'\....O..4...*.| 00000070 14 00 00 00 ff ff ff ff be 40 27 91 84 22 34 47 |.........@'.."4G| 00000080 b9 71 84 b0 27 35 3f 0c 7f aa 01 00 a4 00 00 f8 |.q..'5?.........| 00000090 8c 00 00 19 46 53 50 48 50 00 00 00 00 00 **23** 06 |....FSPHP.....#.| <--- spec version 000000a0 70 65 00 0c 41 44 4c 49 2d 46 53 50 00 f0 06 00 |pe..ADLI-FSP....| -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:17:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/mtrr: Running `remove_temp_solution` for all logical processors
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63498 ) Change subject: cpu/x86/mtrr: Running `remove_temp_solution` for all logical processors ...................................................................... cpu/x86/mtrr: Running `remove_temp_solution` for all logical processors Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4dc9183a06ef60b60907d26ea3e6e382f0c29d8c --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/63498/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 288f06d..a437fb9 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include <cpu/cpu.h> +#include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> @@ -913,11 +914,17 @@ memranges_teardown(&addr_space); } -static void remove_temp_solution(void *unused) +static void restore_original_mtrr_solution(void *unused) { if (put_back_original_solution) commit_var_mtrrs(&mtrr_global_solution); } +static void remove_temp_solution(void *unused) +{ + if (mp_run_on_all_cpus(&restore_original_mtrr_solution, NULL) != CB_SUCCESS) + printk(BIOS_ERR, "MTRR restoring to original solution failure\n"); +} + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, remove_temp_solution, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, remove_temp_solution, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/63498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc9183a06ef60b60907d26ea3e6e382f0c29d8c Gerrit-Change-Number: 63498 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022