coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... Patch Set 3: (12 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63467/comment/52f747e3_52781fcf PS3, Line 13: - Intel PCH-S EDS Vol1 (#621483) This DOC ID is actually vol2 File src/soc/intel/alderlake/gpio_pch_s.c: https://review.coreboot.org/c/coreboot/+/63467/comment/794163e6_afb3507e PS3, Line 15: { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, : { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, : { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, GPP has 4 reset configs in total. Question is how to map it to the outdated values in intelblock header file. Since this is only logical, maybe we should add new names in intelblocks? The valeus would overlap, but at least the names will reflect the real reset configuration https://review.coreboot.org/c/coreboot/+/63467/comment/8272b450_073696ac PS3, Line 70: INTEL_GPP_BASE(GPP_SPI0_IO_2, GPP_C0, GPP_C23, 288), /* GPP_C */ Let's add VPIO3 for completeness INTEL_GPP(GPP_SPI0_IO_2, GPP_VGPIO_PCIE_0, GPP_VGPIO_PCIE_83), https://review.coreboot.org/c/coreboot/+/63467/comment/41284e2f_436a2709 PS3, Line 72: Missing community3 vw entries: GPP_A0 - GPP_A14 GPP_C0 - GPP_C23 https://review.coreboot.org/c/coreboot/+/63467/comment/7e30dfa1_4ec15864 PS3, Line 88: INTEL_GPP(GPP_D0, GPP_JTAG_TDO, GPP_CPU_TRSTB), /* JTAG */ Let's add CPU groups for completeness INTEL_GPP(GPP_D0, GPP_HDACPU_SDI, GPP_C10_WAKE), /* CPU */ https://review.coreboot.org/c/coreboot/+/63467/comment/2db63b28_0727a849 PS3, Line 173: .name = "GPP_SPI0AC", Just GPP_AC https://review.coreboot.org/c/coreboot/+/63467/comment/13029705_7d0128b5 PS3, Line 204: [COMM_5] = { /* GPP D, JTAG */ GPP_D, JTAG, CPU File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/eb22604f_df6d426a PS3, Line 323: #define HOSTSW_OWN_REG_0 0x200 This is 0x150 https://review.coreboot.org/c/coreboot/+/63467/comment/ed66c27c_d1c48111 PS3, Line 324: #define GPI_INT_STS_0 0x220 This is 0x200 https://review.coreboot.org/c/coreboot/+/63467/comment/cd31a2ea_c460c6fe PS3, Line 325: #define GPI_INT_EN_0 0x110 This is 0x220 File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/735ffb85_7865f7e4 PS1, Line 288: #define GPP_F20_IRQ 0x70 : #define GPP_F21_IRQ 0x71 : #define GPP_F22_IRQ 0x72 : #define GPP_F23_IRQ 0x73 : : /* Group D */ : #define GPP_D0_IRQ 0x70 : #define GPP_D1_IRQ 0x71 : #define GPP_D2_IRQ 0x72 : #define GPP_D3_IRQ 0x73 > So does inteltool: […] Yes, ADL PCH-H EDS vol2 says the same File src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/1042e9a7_b5dfb29d PS3, Line 62: #define GPP_GSPI0_CLK_LOOPBK INC(GPP_I17) : #define GPP_GSPI1_CLK_LOOPBK INC(GPP_I18) #define GPP_GSPI0_CLK_LOOPBK INC(GPP_I22) #define GPP_GSPI1_CLK_LOOPBK INC(GPP_GSPI0_CLK_LOOPBK) Right? -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:59:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add GPIO configuration
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63490 to look at the new patch set (#5). Change subject: mb/msi/ms7d25: add GPIO configuration ...................................................................... mb/msi/ms7d25: add GPIO configuration Based on the output of: - inteltool from https://review.coreboot.org/c/coreboot/+/63374 - intelp2m from https://review.coreboot.org/c/coreboot/+/63403 TEST=Build coreboot binary for msi/ms7d5. Actual GPIO setting not tested, as the board does not yet boot past FSP-M. Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A src/mainboard/msi/ms7d25/include/gpio.h M src/mainboard/msi/ms7d25/mainboard.c 2 files changed, 579 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63490/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/msi/ms7d5: add GPIO configuration
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63490 ) Change subject: mb/msi/ms7d5: add GPIO configuration ...................................................................... Patch Set 4: (1 comment) File src/mainboard/msi/ms7d25/mainboard.c: https://review.coreboot.org/c/coreboot/+/63490/comment/ec4de456_5368ddc6 PS2, Line 8: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); > This should be called in the mainboard_silicon_init_params right before FSP silicon init. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:48:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d5: add GPIO configuration
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć. Hello build bot (Jenkins), Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63490 to look at the new patch set (#4). Change subject: mb/msi/ms7d5: add GPIO configuration ...................................................................... mb/msi/ms7d5: add GPIO configuration Based on the output of: - inteltool from https://review.coreboot.org/c/coreboot/+/63374 - intelp2m from https://review.coreboot.org/c/coreboot/+/63403 TEST=Build coreboot binary for msi/ms7d5. Actual GPIO setting not tested, as the board does not yet boot past FSP-M. Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A src/mainboard/msi/ms7d25/include/gpio.h M src/mainboard/msi/ms7d25/mainboard.c 2 files changed, 579 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63490/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/atlas: Configure eSPI IO decode ranges for EC
by Lean Sheng Tan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Christian Walter. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63465 ) Change subject: mb/prodrive/atlas: Configure eSPI IO decode ranges for EC ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63465/comment/4fef8fae_c7f41961 PS2, Line 7: range > nit: plural `ranges` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46 Gerrit-Change-Number: 63465 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:47:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/atlas: Configure eSPI IO decode ranges for EC
by Lean Sheng Tan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Christian Walter, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63465 to look at the new patch set (#4). Change subject: mb/prodrive/atlas: Configure eSPI IO decode ranges for EC ...................................................................... mb/prodrive/atlas: Configure eSPI IO decode ranges for EC This implementation adds eSPI IO decode range for EC. 1. 0x800-0x8FF / 0x200-020F: EC host command range. 2. 0x900-0x9ff: EC memory map range. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46 --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63465/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46 Gerrit-Change-Number: 63465 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/msi/ms7d5: add GPIO configuration
by build bot (Jenkins) (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63490 ) Change subject: mb/msi/ms7d5: add GPIO configuration ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:46:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT
by Kyösti Mälkki (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Philipp Hug, Michał Żygowski, ron minnich, Piotr Król. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63376 ) Change subject: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/poppy/variants/nautilus/sku.c: https://review.coreboot.org/c/coreboot/+/63376/comment/03dca319_41b5edd5 PS3, Line 9: #if ENV_STAGE_DOES_RAMINIT Don't. This is about lack of .data. -- To view, visit https://review.coreboot.org/c/coreboot/+/63376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Gerrit-Change-Number: 63376 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:46:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add basic FSP configuration in devicetree
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63499 ) Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree ...................................................................... mb/msi/ms7d25: add basic FSP configuration in devicetree Configure some basic FSP parameters in devicetree for to allow for booting an OS. Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 69 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63499/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index dccaa25..83405ff 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -1,4 +1,73 @@ chip soc/intel/alderlake + # FSP configuration + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + + # USB Configuration + # TODO: Verify + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c03f1" + register "gen4_dec" = "0x000c0081" + + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + + register "sata_ports_dev_slp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + device domain 0 on device ref igpu on end device ref crashlog off end @@ -10,17 +79,6 @@ device ref heci3 off end device ref heci4 off end device ref sata on end - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end - device ref pcie_rp7 on end - device ref pcie_rp8 on end - device ref pcie_rp9 on end - device ref pcie_rp10 on end - device ref pcie_rp11 on end device ref p2sb on end device ref hda on end device ref smbus on end -- To view, visit https://review.coreboot.org/c/coreboot/+/63499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Gerrit-Change-Number: 63499 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Hello build bot (Jenkins), Michał Żygowski, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63467 to look at the new patch set (#4). Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... soc/intel/alderlake: add GPIO definitions for PCH-S Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol1 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/romstage/fsp_params.c 9 files changed, 1,149 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63467/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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2013

coreboot-gerrit April 2022