coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63493 ) Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... Patch Set 1: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63493/comment/1645ea1e_ab991774 PS1, Line 11: 619015 Did you mean 619501 ADL processors EDS? Patchset: PS1: e File src/soc/intel/alderlake/chipset_pch_s.cb: https://review.coreboot.org/c/coreboot/+/63493/comment/00a4d6f2_44a2685f PS1, Line 4: Missing power limits. PL1 PL2 DOC #619501 Table 15 and 19 common_soc_config.pch_thermal_trip may be 100 as well here https://review.coreboot.org/c/coreboot/+/63493/comment/2bba9a6f_b3f73ed7 PS1, Line 12: device pci 05.0 alias ipu off end Not present on PCH-S https://review.coreboot.org/c/coreboot/+/63493/comment/d0d57ccf_e3e8ca63 PS1, Line 14: device pci 06.2 alias pcie4_1 off end If we talk about ADL-S CPU only, it does not contain PCIe 6.2 (only H, P and U15 lines do). https://review.coreboot.org/c/coreboot/+/63493/comment/0ff75b64_12ebd152 PS1, Line 19: device pci 12.0 alias ish off end pci 11.0 uart3 https://review.coreboot.org/c/coreboot/+/63493/comment/611f407b_47d2f457 PS1, Line 25: device usb 0.0 alias xhci_root_hub off : chip drivers/usb/acpi : device usb 2.0 alias usb2_port1 off end : end : chip drivers/usb/acpi : device usb 2.1 alias usb2_port2 off end : end : chip drivers/usb/acpi : device usb 2.2 alias usb2_port3 off end : end : chip drivers/usb/acpi : device usb 2.3 alias usb2_port4 off end : end : chip drivers/usb/acpi : device usb 2.4 alias usb2_port5 off end : end : chip drivers/usb/acpi : device usb 2.5 alias usb2_port6 off end : end : chip drivers/usb/acpi : device usb 2.6 alias usb2_port7 off end : end : chip drivers/usb/acpi : device usb 2.7 alias usb2_port8 off end : end : chip drivers/usb/acpi : device usb 2.8 alias usb2_port9 off end : end : chip drivers/usb/acpi : device usb 2.9 alias usb2_port10 off end : end : chip drivers/usb/acpi : device usb 3.0 alias usb3_port1 off end : end : chip drivers/usb/acpi : device usb 3.1 alias usb3_port2 off end : end : chip drivers/usb/acpi : device usb 3.2 alias usb3_port3 off end : end : chip drivers/usb/acpi : device usb 3.3 alias usb3_port4 off end : end : end 10 USB 3.x ports and 14 USB2.0 ports -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:10:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Eric Lai (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Amanda Hwang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63495 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: please add signed-off -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:00:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 6: (2 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/63293/comment/80efaaf3_faf6baf0 PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. > Hmm, the CL just facilitates to modify PmcUsb2PhySusPgEnable UPD. […] Ack https://review.coreboot.org/c/coreboot/+/63293/comment/991ebd03_f7285753 PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. > Hmm, the CL just facilitates to modify PmcUsb2PhySusPgEnable UPD. […] Added the comment as per request so that the comment will be visible if someone experience the same issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Angel Pons, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63293 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from devicetree. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > > > > ah yes, thanks for capturing this. > > > > > i miss this. > > > > > it only restores BSP MTRR. > > > > > > > > @Arthur, can you please comment reg CB:63498 > > > > > > With TXT APs are shut down along the way and not started up again. I know it's a different problem that also needs a solution, but that approach would break it. > > > > oops I was not aware of that. > > > > > > > > What do you think of my suggestion to add a nop call on APs, to be sure they finished setting up MTRRs and don't override that temp one. Then the temp MTRR is only set on the BSP? > > > > this would work bt isn't MTRR is shared between logical processors belongs to a core. > > Is it so bad that one AP also has the temp MTRR? when the BSP removes that temp MTRR that would also be resolved. > > > > > > I generally like to avoid keeping track of the state of APs. > > > > yeah, that would be complicated. I believe Kane has captured some log, that shows the different core vs. logical processor snapshot. @kane, can you please comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:52:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/{brya, brask}: Disable PCH USB2 phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/{brya, brask}: Disable PCH USB2 phy power gating ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63294/comment/3269f9d2_048fe985 PS4, Line 10: to prevent possible display flicker issue > Correct, theoretical possibility and we have noticed the issue from few boards! Ack File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/63294/comment/70a8b389_1bbc3093 PS5, Line 25: t > typo: Remove `t` Ack https://review.coreboot.org/c/coreboot/+/63294/comment/4a79ea1f_9b43b60a PS5, Line 25: the > nit: Remove `the` Ack File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb: https://review.coreboot.org/c/coreboot/+/63294/comment/7c6d9616_f27dd993 PS5, Line 25: # As per Intel Advistory doc#723158, the change is required to prevent the possible > Same comments as on Brask Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:49:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by build bot (Jenkins) (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 6: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:49:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/{brya, brask}: Disable PCH USB2 phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sridhar Siricilla. Hello build bot (Jenkins), Subrata Banik, Paul Menzel, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63294 to look at the new patch set (#6). Change subject: mb/google/{brya, brask}: Disable PCH USB2 phy power gating ...................................................................... mb/google/{brya, brask}: Disable PCH USB2 phy power gating The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63294/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 5: (1 comment) Patchset: PS2: > Sure, I will add in other CL where . Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022