coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans. Subrata Banik has uploaded a new patch set (#3) to the change originally created by Kane Chen. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... soc/intel/common: Enable rom cache on all CPU threads In the previous implementation, it asks all CPUs/threads to run _x86_setup_mtrrs and BSP to run post_cpus_add_romcache. However the BSP doesn't wait all threads to finish _x86_setup_mtrrs and run post_cpus_add_romcache immediately. It causes a race condition that other thread in same core could finish _x86_setup_mtrrs later than post_cpus_add_romcache run by BSP. MTRR is a core level MSR, so settings in post_cpus_add_romcache could be overriden unexpectedly by other thread in the same core. Ex: Core0, thread 1 finishes _x86_setup_mtrrs later than post_cpus_add_romcache run by bsp Core0 thread 0. Instead of using different MTRRs settings on BSP/APs and cause race conditionm, this patch asks all cpu/threads to run post_cpus_add_romcache, so that MTRRs on all cores are aligned. This patch also calls need_restore_mtrr to set put_back_original_solution in order to restor mtrr later in remove_temp_solution. BUG=b:225766934 TEST=Tested on gimble and found rom cache is set properly right before payload lzma decompress and restored to original mtrr in the end of coreboot Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63486/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Amanda Hwang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63495 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63456 ) Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Tim, I have selected DISPLAY_FSP_HEADER and it clearly shows FSP v2.3: [SPEW ] Spec version: v2.3 [SPEW ] Revision: 12.0.101, Build Number 112 [SPEW ] Type: release/official [SPEW ] image ID: $ADLFSP$ [SPEW ] base 0xff120000 + 0xb0000 [SPEW ] Config region 0xa384c + 0xb40 [SPEW ] Memory init offset 0x210 We don't know what the target spec version will be. If it occurs to be v2.2 in the end, we can always revert the commit quickly when FSP for ADL-S is published. -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:11:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63496 to look at the new patch set (#2). Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 Based on the latest schematic, change MAX98360 AMP interface from I2S2 to I2S1 due to Intel BT offload concern. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: Ib11c5ef9583fbc623adf239db60327a7a4926995 --- M src/mainboard/google/brya/variants/brya0/fw_config.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/63496/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11c5ef9583fbc623adf239db60327a7a4926995 Gerrit-Change-Number: 63496 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add support to update the FIVR configs
by V Sowmya (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63497 ) Change subject: soc/intel/alderlake: Add support to update the FIVR configs ...................................................................... soc/intel/alderlake: Add support to update the FIVR configs This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 --- M src/soc/intel/alderlake/chip.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/63497/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 2dae9cd..2f48361 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -82,7 +82,7 @@ /* * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2, - * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 + * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT4:S0. */ enum fivr_enable_states { FIVR_ENABLE_S0i1_S0i2 = BIT(0), @@ -90,6 +90,7 @@ FIVR_ENABLE_S3 = BIT(2), FIVR_ENABLE_S4 = BIT(3), FIVR_ENABLE_S5 = BIT(4), + FIVR_ENABLE_S0 = BIT(5), }; /* @@ -107,7 +108,7 @@ }; #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ - FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) + FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5 | FIVR_ENABLE_S0) /* * The Max Pkg Cstate * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, -- To view, visit https://review.coreboot.org/c/coreboot/+/63497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 Gerrit-Change-Number: 63497 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Jakub Czapiga (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Balaji Manigandan. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63240/comment/a17a6c30_8900ffbb PS3, Line 9: #3461454 > Does it mean CONFIG_LP_CHROMEOS=y has to be set in depthcharge board/<BOARD>/defconfig ? It's depthcharge-specific config, it does not affect libpayload at all (and should not contain CONFIG_LP_* entries anyway). Depthcharge includes libpayload's config.h/.config, which was generated and installed in it's build environment (ChromeOS SDK). In CrOS-SDK libpayloads' configs contain CONFIG_LP_CHROMEOS=y. Setting it in depthcharge/board/<BOARD>/defconfig will not change anything in libpayload, because it is compiled before depthcharge. So, depthcharge should be build with libpayload compiled with CONFIG_LP_CHROMEOS=y, which will enable CONFIG_LP_LIB_VBOOT=y and some other things required by it. But it does not mean, that these components should be in defconfig. vBoot is not required by other payloads and I do not think that it will change soon. It would create unnecessary overhead for others using libpayload. If you want to build any payload, you have to tune config for it. defconfig is here to make libpayload usable for general cases, and depthcharge is not one of them. -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 3 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:00:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by build bot (Jenkins) (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63495 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/brya/variants/brya0/fw_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145865): https://review.coreboot.org/c/coreboot/+/63495/comment/09aea8db_06ef71cb PS1, Line 126: } else if(!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145865): https://review.coreboot.org/c/coreboot/+/63495/comment/e687fd86_b10279f7 PS1, Line 126: } else if(!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))){ space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145865): https://review.coreboot.org/c/coreboot/+/63495/comment/a10a7406_82ddb2fc PS1, Line 145: gpio_configure_pads(i2s_max98360_enable_pads, ARRAY_SIZE(i2s_max98360_enable_pads)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 10:00:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63496 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 Based on the latest schematic, change MAX98360 AMP interface from I2S2 to I2S1 due to Intel BT offload concern. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: Ib11c5ef9583fbc623adf239db60327a7a4926995 --- M src/mainboard/google/brya/variants/brya0/fw_config.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/63496/1 diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index 999264a..4a23db9 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -123,7 +123,7 @@ gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); - } else if(!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))){ + } else if (!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { printk(BIOS_INFO, "BT offload disabled\n"); gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); -- To view, visit https://review.coreboot.org/c/coreboot/+/63496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11c5ef9583fbc623adf239db60327a7a4926995 Gerrit-Change-Number: 63496 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Amanda Hwang (Code Review) 08 Apr '22

08 Apr '22

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63495 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 --- M src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63495/1 diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index e1c6f89..999264a 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -26,6 +26,19 @@ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), /* SDW_SPKR_DATA */ }; +static const struct pad_config i2s_max98360_enable_pads[] = { + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA1_R */ + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + static const struct pad_config sndw_disable_pads[] = { PAD_NC(GPP_S0, NONE), PAD_NC(GPP_S1, NONE), @@ -110,7 +123,7 @@ gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); - } else { + } else if(!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))){ printk(BIOS_INFO, "BT offload disabled\n"); gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); @@ -127,9 +140,11 @@ enable_i2s(); } - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S_AMP_SSP2))) { + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); - enable_i2s(); + gpio_configure_pads(i2s_max98360_enable_pads, ARRAY_SIZE(i2s_max98360_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index e566067..fd8224c 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -17,7 +17,7 @@ option MAX98373_ALC5682_SNDW 2 option MAX98373_NAU88L25B_I2S 3 option ALC1019_NAU88L25B_I2S 4 - option MAX98360_ALC5682I_I2S_AMP_SSP2 5 + option MAX98360_ALC5682I_I2S 5 end field DB_LTE 11 12 option LTE_ABSENT 0 @@ -255,7 +255,7 @@ register "property_list[0].integer" = "1" device i2c 1a on probe AUDIO MAX98357_ALC5682I_I2S - probe AUDIO MAX98360_ALC5682I_I2S_AMP_SSP2 + probe AUDIO MAX98360_ALC5682I_I2S end end chip drivers/i2c/nau8825 @@ -619,7 +619,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" device generic 0 on - probe AUDIO MAX98360_ALC5682I_I2S_AMP_SSP2 + probe AUDIO MAX98360_ALC5682I_I2S end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 9: (3 comments) File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/63251/comment/8e1635e2_9d286ad1 PS8, Line 91: struct cb_pcie pcie_info; > Copying whole coreboot table entries in here isn't great (I guess we were lazy for the framebuffer b […] Done File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/b06c29e2_9ea85251 PS8, Line 176: uint64_t atu_base; /* Base address of Address translation unit */ > You should really use struct lb_uint64 for all of these to avoid unintentional padding differences b […] Done, I add a new patch to convert it: https://review.coreboot.org/c/coreboot/+/63494 File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/63251/comment/6882619f_3486409b PS8, Line 136: lb_pcie->config_size = pcie->config_size; > Sorry, but something looks off here. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 09:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022