coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Angel Pons, Kane Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: @Sridhar, can you please address the opens ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 07:36:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/{brya, brask}: Disable PCH USB2 phy power gating
by Subrata Banik (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/{brya, brask}: Disable PCH USB2 phy power gating ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 07:36:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski, Maxim Polyakov, Angel Pons. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake macro generation ...................................................................... Patch Set 4: (5 comments) File util/intelp2m/description.md: https://review.coreboot.org/c/coreboot/+/63403/comment/9f93b594_82da217f PS1, Line 39: AlderLake-H > In order for intelp2m to work correctly for all variants of the Adler Lake family, it is necessary t […] Added missing pad group names to the list in KeywordsCheck. File util/intelp2m/description.md: https://review.coreboot.org/c/coreboot/+/63403/comment/0ddb1e7e_957a5acd PS3, Line 39: AlderLake-H > Alder Lake? Done File util/intelp2m/gpio_adl_h.h: PS3: > Unnecessary file Done File util/intelp2m/platforms/adl/macro.go: https://review.coreboot.org/c/coreboot/+/63403/comment/0f56a9e3_9905c7e9 PS3, Line 99: macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro : cnl.PlatformSpecific{}}, : fields.InterfaceGet()) > macro := common.GetInstanceMacro( […] Applied, still same issue though: ``` $ ./intelp2m -file ~/inteltool.log -iiii -fld cb -p adl -o gpio_adl_h.h 1 msi_pro_z690_a/intelp2m_adl!? Info level: Use level 4! Log file: /home/mkopec/inteltool.log Output generated file: gpio_adl_h.h Parse IntelTool Log File... panic: runtime error: invalid memory address or nil pointer dereference [signal SIGSEGV: segmentation violation code=0x1 addr=0x18 pc=0x4c2bd8] goroutine 1 [running]: _/home/mkopec/Development/Dasharo/coreboot/util/intelp2m/platforms/cnl.PlatformSpecific.KeywordCheck(...) /home/mkopec/Development/Dasharo/coreboot/util/intelp2m/platforms/cnl/template.go:23 _/home/mkopec/Development/Dasharo/coreboot/util/intelp2m/platforms/adl.PlatformSpecific.KeywordCheck(...) /home/mkopec/Development/Dasharo/coreboot/util/intelp2m/platforms/adl/template.go:24 _/home/mkopec/Development/Dasharo/coreboot/util/intelp2m/parser.(*ParserData).Parse(0xc000080f10) /home/mkopec/Development/Dasharo/coreboot/util/intelp2m/parser/parser.go:236 +0x7a3 main.main() /home/mkopec/Development/Dasharo/coreboot/util/intelp2m/main.go:137 +0x8c9 ``` File util/intelp2m/platforms/adlh/macro.go: https://review.coreboot.org/c/coreboot/+/63403/comment/8284b630_e0a7a237 PS2, Line 20: MAX_DW_NUM = common.MAX_DW_NUM > Are DW2 and DW3 values contained in the GPIO registers dump from inteltool for this platforms? […] They aren't. Here's a sample of inteltool output: ``` CPU: ID 0x90672, Processor Type 0x0, Family 0x6, Model 0x97, Stepping 0x2 Northbridge: 8086:4648 (12th generation (Alder Lake S family) Core Processor (Desktop)) Southbridge: 8086:7a84 (Z690) IGD: 8086:4680 (Intel(R) AlderLake-S GT1) SBREG_BAR = 0xe0000000 (MEM) ============= GPIOS ============= ------- GPIO Community 0 ------- PCR Port ID: 0x6e0000 ------- GPIO Group GPP_I ------- 0x0700: 0x0000001884000102 GPP_I0 GPIO 0x0710: 0x0000001984000500 GPP_I1 DDSP_HPD1 0x0720: 0x0000001a84000500 GPP_I2 DDSP_HPD2 0x0730: 0x0000001b84000502 GPP_I3 DDSP_HPD3 0x0740: 0x0000001c84000500 GPP_I4 DDSP_HPD4 0x0750: 0x0000001d84000500 GPP_I5 DDPB_CTRLCLK 0x0760: 0x0000001e84000500 GPP_I6 DDPB_CTRLDATA 0x0770: 0x0000002084000500 GPP_I7 DDPC_CTRLCLK 0x0780: 0x0000002184000500 GPP_I8 DDPC_CTRLDATA 0x0790: 0x0000002284000102 GPP_I9 GPIO 0x07a0: 0x0000002384000102 GPP_I10 GPIO 0x07b0: 0x0000002484000502 GPP_I11 USB_OC4# 0x07c0: 0x0000002584000502 GPP_I12 USB_OC5# 0x07d0: 0x0000002684000502 GPP_I13 USB_OC6# 0x07e0: 0x0000002784000502 GPP_I14 USB_OC7# 0x07f0: 0x0000002884000102 GPP_I15 GPIO 0x0800: 0x0000002984000102 GPP_I16 GPIO 0x0810: 0x0000002a84000102 GPP_I17 GPIO 0x0820: 0x0000002b84000102 GPP_I18 GPIO 0x0830: 0x0000002c84000102 GPP_I19 GPIO 0x0840: 0x0000002d84000102 GPP_I20 GPIO 0x0850: 0x0000002e84000102 GPP_I21 GPIO 0x0860: 0x0000003084000102 GPP_I22 GPIO 0x0870: 0x0000000040000700 GSPI0_CLK_LOOPBK GSPI0_CLK_LOOPBK 0x0880: 0x0000000040000700 GSPI1_CLK_LOOPBK GSPI1_CLK_LOOPBK ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 07:35:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Angel Pons. Hello build bot (Jenkins), Michał Żygowski, Maxim Polyakov, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63403 to look at the new patch set (#4). Change subject: util/intelp2m: Add support for Alder Lake macro generation ...................................................................... util/intelp2m: Add support for Alder Lake macro generation Add support for Alder Lake as a separate parsing profile, copying the existing 'Cannon' profile and adjusting for differences in reset mapping and GPIO macro generation. TEST=Generate GPIO macros for MSI PRO Z690-A Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M util/intelp2m/config/config.go M util/intelp2m/description.md M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/adl/macro.go A util/intelp2m/platforms/adl/template.go 6 files changed, 153 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63403/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Kane Chen (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63486/comment/22051300_a404346b PS2, Line 11: However the BSP doesn't wait all threads to finish _x86_setup_mtrrs > I think it's better to fix this than to program something temporary on APs too. […] appreciate your suggestion:) let me do some experiments . Patchset: PS2: > Is restoring the temp mtrr also done APs. I thought it didn't. ah yes, thanks for capturing this. i miss this. it only restores BSP MTRR. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 07:25:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d5: add GPIO configuration
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63490 ) Change subject: mb/msi/ms7d5: add GPIO configuration ...................................................................... mb/msi/ms7d5: add GPIO configuration Based on the output of: - inteltool from https://review.coreboot.org/c/coreboot/+/63374 - intelp2m from https://review.coreboot.org/c/coreboot/+/63403 TEST=Build coreboot binary for msi/ms7d5. Actual GPIO setting not tested, as the board does not yet boot past FSP-M. Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A src/mainboard/msi/ms7d25/include/gpio.h M src/mainboard/msi/ms7d25/mainboard.c 2 files changed, 574 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63490/1 diff --git a/src/mainboard/msi/ms7d25/include/gpio.h b/src/mainboard/msi/ms7d25/include/gpio.h new file mode 100644 index 0000000..9a3fcb6 --- /dev/null +++ b/src/mainboard/msi/ms7d25/include/gpio.h @@ -0,0 +1,572 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + + /* GPP_I0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI), + /* GPP_I1 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + /* GPP_I2 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + /* GPP_I3 - DDSP_HPD3 */ + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + /* GPP_I4 - DDSP_HPD4 */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + /* GPP_I5 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + /* GPP_I6 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + /* GPP_I7 - DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + /* GPP_I8 - DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + /* GPP_I9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI), + /* GPP_I10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI), + /* GPP_I11 - USB_OC4# */ + PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1), + /* GPP_I12 - USB_OC5# */ + PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1), + /* GPP_I13 - USB_OC6# */ + PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1), + /* GPP_I14 - USB_OC7# */ + PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1), + /* GPP_I15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI), + /* GPP_I16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI), + /* GPP_I17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI), + /* GPP_I18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI), + /* GPP_I19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, PLTRST, OFF, ACPI), + /* GPP_I20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, PLTRST, OFF, ACPI), + /* GPP_I21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, PLTRST, OFF, ACPI), + /* GPP_I22 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF1), + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, PLTRST, NF1), + /* GPP_R5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI), + /* GPP_R6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI), + /* GPP_R7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI), + /* GPP_R8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI), + /* GPP_R9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI), + /* GPP_R10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI), + /* GPP_R11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI), + /* GPP_R12 - DDP3_CTRLCLK */ + PAD_CFG_NF(GPP_R12, NONE, PLTRST, NF2), + /* GPP_R13 - DDP3_CTRLDATA */ + PAD_CFG_NF(GPP_R13, NONE, PLTRST, NF2), + /* GPP_R14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI), + /* GPP_R15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI), + /* GPP_R16 - DDP1_CTRLCLK */ + PAD_CFG_NF(GPP_R16, NONE, PLTRST, NF1), + /* GPP_R17 - DDP1_CTRLDATA */ + PAD_CFG_NF(GPP_R17, NONE, PLTRST, NF1), + /* GPP_R18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R18, NONE, PLTRST, OFF, ACPI), + /* GPP_R19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R19, NONE, PLTRST, OFF, ACPI), + /* GPP_R20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI), + /* GPP_R21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_J ------- */ + + /* GPP_J0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, PLTRST, OFF, ACPI), + /* GPP_J1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J1, NONE, PLTRST, OFF, ACPI), + /* GPP_J2 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_J2, NONE, PLTRST, NF1), + /* GPP_J3 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_J3, NONE, PLTRST, NF1), + /* GPP_J4 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_J4, NONE, PLTRST, NF1), + /* GPP_J5 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_J5, NONE, PLTRST, NF1), + /* GPP_J6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI), + /* GPP_J7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, PLTRST, OFF, ACPI), + /* GPP_J8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J8, NONE, PLTRST, OFF, ACPI), + /* GPP_J9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, PLTRST, OFF, ACPI), + /* GPP_J10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI), + /* GPP_J11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI), + /* GPP_B1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI), + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, PLTRST, OFF, ACPI), + /* GPP_B3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), + /* GPP_B4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI), + /* GPP_B5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), + /* GPP_B6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), + /* GPP_B7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), + /* GPP_B8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI), + /* GPP_B9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI), + /* GPP_B10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI), + /* GPP_B11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + /* GPP_B15 - GPIO */ + PAD_CFG_GPO(GPP_B15, 0, PLTRST), + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, PLTRST), + /* GPP_B17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI), + /* GPP_B18 - PMCALERT# */ + PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), + /* GPP_B19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, PLTRST, OFF, ACPI), + /* GPP_B20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI), + /* GPP_B21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI), + /* GPP_B22 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI), + /* GPP_B23 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + PAD_CFG_GPO(GPP_G0, 0, PLTRST), + /* GPP_G1 - GPIO */ + PAD_CFG_GPO(GPP_G1, 1, RSMRST), + /* GPP_G2 - DNX_FORCE_RELOAD */ + PAD_CFG_NF(GPP_G2, NONE, PLTRST, NF1), + /* GPP_G3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), + /* GPP_G4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), + /* GPP_G5 - SLP_DRAM# */ + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), + /* GPP_G6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), + /* GPP_G7 - GPIO */ + PAD_NC(GPP_G7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), + /* GPP_H1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), + /* GPP_H2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, PLTRST, OFF, ACPI), + /* GPP_H4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), + /* GPP_H5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H5, NONE, PLTRST, OFF, ACPI), + /* GPP_H6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, PLTRST, OFF, ACPI), + /* GPP_H7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI), + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI), + /* GPP_H9 - SRCCLKREQ15# */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI), + /* GPP_H11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI), + /* GPP_H12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI), + /* GPP_H13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI), + /* GPP_H14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI), + /* GPP_H15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), + /* GPP_H16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), + /* GPP_H17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), + /* GPP_H18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), + /* GPP_H19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), + /* GPP_H20 - GPIO */ + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + /* GPP_H21 - GPIO */ + PAD_CFG_GPO(GPP_H21, 0, PLTRST), + /* GPP_H22 - GPIO */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + /* GPP_H23 - GPIO */ + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, NONE, PLTRST, NF1), + /* GPD1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PLTRST, OFF, ACPI), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NONE, PLTRST, NF1), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, NONE, PLTRST, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PLTRST, NF1), + /* GPD7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PLTRST, OFF, ACPI), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PLTRST, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, PLTRST, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), + /* GPD11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD11, NONE, PLTRST, OFF, ACPI), + /* GPD12 - GPIO */ + PAD_CFG_TERM_GPO(GPD12, 1, DN_5K, RSMRST), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1), + /* GPP_A5 - ESPI_CLK */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + /* GPP_A6 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + /* GPP_A7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), + /* GPP_A8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI), + /* GPP_A9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI), + /* GPP_A10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, PLTRST, OFF, ACPI), + /* GPP_A11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI), + /* GPP_A13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI), + /* GPP_A14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, PLTRST, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, PLTRST, NF1), + /* GPP_C2 - SMBALERT# */ + PAD_CFG_NF(GPP_C2, NONE, PLTRST, NF1), + /* GPP_C3 - GPIO */ + PAD_CFG_GPO(GPP_C3, 1, PLTRST), + /* GPP_C4 - GPIO */ + PAD_CFG_GPO(GPP_C4, 1, PLTRST), + /* GPP_C5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI), + /* GPP_C6 - GPIO */ + PAD_CFG_GPO(GPP_C6, 0, PLTRST), + /* GPP_C7 - GPIO */ + PAD_CFG_GPO(GPP_C7, 0, PLTRST), + /* GPP_C8 - GPIO */ + PAD_CFG_GPO(GPP_C8, 1, RSMRST), + /* GPP_C9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), + /* GPP_C10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), + /* GPP_C11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI), + /* GPP_C12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI), + /* GPP_C13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI), + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI), + /* GPP_C15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI), + /* GPP_C16 - I2C0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + /* GPP_C17 - I2C0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + /* GPP_C18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), + /* GPP_C19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), + /* GPP_C20 - GPIO */ + PAD_CFG_GPO(GPP_C20, 0, PLTRST), + /* GPP_C21 - GPIO */ + PAD_CFG_GPO(GPP_C21, 0, PLTRST), + /* GPP_C22 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI), + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI), + /* GPP_S1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI), + /* GPP_S2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI), + /* GPP_S3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI), + /* GPP_S4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI), + /* GPP_S5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI), + /* GPP_S6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI), + /* GPP_S7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - SATAXPCIE0 */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), + /* GPP_E1 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), + /* GPP_E2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), + /* GPP_E3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI), + /* GPP_E4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, PLTRST, OFF, ACPI), + /* GPP_E5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI), + /* GPP_E6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI), + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), + /* GPP_E8 - SATALED# */ + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + /* GPP_E9 - USB_OC0# */ + PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), + /* GPP_E10 - USB_OC1# */ + PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), + /* GPP_E11 - USB_OC2# */ + PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), + /* GPP_E12 - USB_OC3# */ + PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI), + /* GPP_E14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI), + /* GPP_E15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI), + /* GPP_E16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), + /* GPP_E17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI), + /* GPP_E18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI), + /* GPP_E19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, PLTRST, OFF, ACPI), + /* GPP_E20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI), + /* GPP_E21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_K ------- */ + + /* GPP_K0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, PLTRST, OFF, ACPI), + /* GPP_K1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI), + /* GPP_K2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, PLTRST, OFF, ACPI), + /* GPP_K3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI), + /* GPP_K4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI), + /* GPP_K5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI), + /* GPP_K6 - n/a */ + PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2), + /* GPP_K7 - n/a */ + PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2), + /* GPP_K8 - CORE_VID0 */ + PAD_CFG_NF(GPP_K8, NONE, PLTRST, NF1), + /* GPP_K9 - CORE_VID1 */ + PAD_CFG_NF(GPP_K9, NONE, PLTRST, NF1), + /* GPP_K10 - n/a */ + PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2), + /* GPP_K11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI), + /* GPP_F1 - GPIO */ + PAD_CFG_GPI_SCI(GPP_F1, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_F2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI), + /* GPP_F3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), + /* GPP_F4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), + /* GPP_F5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), + /* GPP_F6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), + /* GPP_F7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), + /* GPP_F8 - SATA_DEVSLP6 */ + PAD_CFG_NF(GPP_F8, NONE, PLTRST, NF1), + /* GPP_F9 - SATA_DEVSLP7 */ + PAD_CFG_NF(GPP_F9, NONE, PLTRST, NF1), + /* GPP_F10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), + /* GPP_F11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), + /* GPP_F12 - GPIO */ + PAD_CFG_GPO(GPP_F12, 1, RSMRST), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), + /* GPP_F14 - PS_ON# */ + PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1), + /* GPP_F15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI), + /* GPP_F16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI), + /* GPP_F17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + /* GPP_F18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI), + /* GPP_F19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI), + /* GPP_F20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI), + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI), + /* GPP_F22 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI), + /* GPP_F23 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, PLTRST, OFF, ACPI), + /* GPP_D1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), + /* GPP_D2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + /* GPP_D4 - SML1CLK */ + PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), + /* GPP_D5 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF2), + /* GPP_D6 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3), + /* GPP_D7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), + /* GPP_D8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), + /* GPP_D9 - SML0CLK */ + PAD_CFG_NF(GPP_D9, NONE, PLTRST, NF1), + /* GPP_D10 - SML0DATA */ + PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1), + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI), + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI), + /* GPP_D13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), + /* GPP_D14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI), + /* GPP_D15 - SML1DATA */ + PAD_CFG_NF(GPP_D15, NONE, PLTRST, NF1), + /* GPP_D16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI), + /* GPP_D17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI), + /* GPP_D18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI), + /* GPP_D19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI), + /* GPP_D20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI), + /* GPP_D21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI), + /* GPP_D22 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI), + /* GPP_D23 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), +}; diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index ac6b252..5d9cc32 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include "include/gpio.h" static void mainboard_init(void *chip_info) { - + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Hello Michał Żygowski, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63467 to look at the new patch set (#2). Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... soc/intel/alderlake: add GPIO definitions for PCH-S Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol1 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/romstage/fsp_params.c 9 files changed, 1,149 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63467/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Taniya Das, Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 7: (1 comment) File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/cc859ca9_66e781ab PS6, Line 425: return clock_configure((struct clock_rcg *) > Ok this is a good point. […] Assigned mdss_clk_cfg.hz. -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 06:53:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Arthur Heymans (Code Review) 08 Apr '22

08 Apr '22

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Arthur Heymans (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Kane Chen. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63486/comment/ca1fba5b_dc07e566 PS2, Line 11: However the BSP doesn't wait all threads to finish _x86_setup_mtrrs I think it's better to fix this than to program something temporary on APs too. It's already hard enough to keep track of what is going on, on the BSP ;-) Maybe you can add another AP call with a NOOP function to make sure that they all completed the previous call? Patchset: PS2: Is restoring the temp mtrr also done APs. I thought it didn't. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 06:52:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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