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Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches
......................................................................
Patch Set 7:
(2 comments)
File src/soc/qualcomm/common/clock.c:
https://review.coreboot.org/c/coreboot/+/63289/comment/d94b41c9_abd077c7
PS6, Line 104: die("Failed to find a matching clock frequency!\n");
> You should print hz and the clk (rcg) pointer in this message so it's possible to understand what ex […]
Done
File src/soc/qualcomm/sc7280/clock.c:
https://review.coreboot.org/c/coreboot/+/63289/comment/b362825d_78be9a78
PS6, Line 425: return clock_configure((struct clock_rcg *)
> Does this work? Note that this function never initializes mdss_clk_cfg. […]
Ok this is a good point. This function is actually not called yet (until CB:61342), so it didn't throw an error when testing.
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Change subject: arch/x86/tables.c: Increase MAX_SMBIOS_SIZE
......................................................................
Patch Set 2: Code-Review+1
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Hello build bot (Jenkins), Taniya Das, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63289
to look at the new patch set (#7).
Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches
......................................................................
soc/qualcomm/common: Make clock_configure() check for exact matches
Previously, clock_configure() will configure the clocks to round up to
the next highest frequency bin. This seems non-intuitive. Changing
the logic to find an exact frequency match and will halt booting if
not found. Recently fixed a bug in CB:63311, where the clock was
being set incorrectly for emmc and was able to find it because of this
stricter check.
BUG=b:198627043
BRANCH=None
TEST=build herobrine image and try to set SPI frequency to number not
supported. Ensure device doesn't boot.
Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/soc/qualcomm/common/clock.c
M src/soc/qualcomm/common/include/soc/clock_common.h
M src/soc/qualcomm/sc7180/clock.c
M src/soc/qualcomm/sc7280/clock.c
4 files changed, 23 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63289/7
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 )
Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62856/comment/e388a1c6_3140e001
PS7, Line 9: UFS (Universal Flash Storage) is the next generation storage
: standard and a SCSI storage technology. It is also a successor
: of eMMC.
Please reflow for 72 characters per line.
https://review.coreboot.org/c/coreboot/+/62856/comment/110855ba_4d3e8704
PS7, Line 15: 2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb
Why can’t coreboot enable this controller? Or is it just to make the PCIe(?) device visible?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62913 )
Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N
......................................................................
Patch Set 10:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62913/comment/41b45649_f357c155
PS10, Line 9: Alder Lake N
I believe, the official spelling is Alder Lake-N. (If true, also one occurrence below.)
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62913/comment/c1163a9c_580b4094
PS10, Line 52: AlderLake
Alder Lake
https://review.coreboot.org/c/coreboot/+/62913/comment/b2ec947a_0fb5c8e2
PS10, Line 53: Alder Lake N
I think the official spelling is Alder Lake-N.
https://review.coreboot.org/c/coreboot/+/62913/comment/e75fdad3_762795aa
PS10, Line 58: (CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||
: CONFIG(BOARD_INTEL_ADLRVP_N))
Is this already a boolean, or, if not, can !! be prepended to make it one? No ternary operator needed then.
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Hello Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62969
to look at the new patch set (#2).
Change subject: mb/google/rex: Add MTL reference platform
......................................................................
mb/google/rex: Add MTL reference platform
This commit is a stub for rex, which is a an Intel Meteor Lake-P
reference platform.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6
---
A src/mainboard/google/rex/Kconfig
A src/mainboard/google/rex/Kconfig.name
A src/mainboard/google/rex/board_info.txt
A src/mainboard/google/rex/dsdt.asl
A src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
5 files changed, 61 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/62969/2
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