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Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/eve/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/7cad7fc6_2dcd622e
PS6, Line 26: CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
> Yes, that is true, I am not sure if/why these are still required anymore, because crossystem will fa […]
Actually, I meant if the use of line above with CROS_GPIO_VIRTUAL was still valid, I can see recovery_mode_switch filled in vboot context, and entry in CRHW.GPIO appears to be unusable as it does not store the state.
As for WP, I do not see VBSD_BOOT_FIRMWARE_WP_ENABLED being set anywhere, and only mrc_cache code calls get_write_protect_state().
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63441
to look at the new patch set (#2).
Change subject: mb/google/brya/var/vell: camera LED flicker problem
......................................................................
mb/google/brya/var/vell: camera LED flicker problem
BUG=b:219644184
TEST=Build and boot on vell, observe whether camera LED flicker
Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63441/2
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Change subject: mb/google,samsung: Drop init_bootmode_straps()
......................................................................
Patch Set 4:
(2 comments)
File src/include/bootmode.h:
https://review.coreboot.org/c/coreboot/+/59008/comment/6c9bc34c_66d76042
PS2, Line 19: void stash_bootmode(int flag_spi_wp, int flag_rec_mode);
> IIRC our official instructions to users have always been "hold down the recovery button until you se […]
Ack
File src/mainboard/google/beltino/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59008/comment/413532be_62d6687d
PS3, Line 16: !get_recovery_mode_switch(), "presence"},
> In depthcharge, for GPIO_REC_MODE we only ever cared about the value that was sampled by coreboot -- […]
Well get_recovery_mode_switch() is sampled src/security/vboot/vboot_logic.c and the lb_gpio identifier string "presence" has no longer been placed there for ages.
So I was hoping to have a reason to drop any remaining "presence" entries as superseded by vboot context.
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Change subject: mb/google,samsung: Drop init_bootmode_straps()
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
File src/include/bootmode.h:
https://review.coreboot.org/c/coreboot/+/59008/comment/57099f3f_eb411973
PS2, Line 19: void stash_bootmode(int flag_spi_wp, int flag_rec_mode);
> At least for samsung/lumpy, rec mode switch is momentary push button. […]
IIRC our official instructions to users have always been "hold down the recovery button until you see the recovery screen appear", so they should really be no reason to read it in romstage vs. ramstage.
File src/mainboard/google/beltino/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59008/comment/b919984e_11b1014a
PS3, Line 16: !get_recovery_mode_switch(), "presence"},
> Does the initial state sampled late in ramstage have any significance? We're adding an actual GPIO p […]
In depthcharge, for GPIO_REC_MODE we only ever cared about the value that was sampled by coreboot -- we ignored the actual GPIO pin info. Depthcharge used to differentiate between GPIOs that should get resampled at runtime (like "lid", "power", "EC in RW") and those where it just uses the value from coreboot (like "recovery" or "write protect") because they're not expected to change in the middle of a single boot. Today we don't use most of these GPIOs anymore and I believe only the former category is left in practice on the boards we still support in depthcharge ToT.
However, for boards that still booted u-boot (if we still care about having ToT coreboot stay compatible to that), I don't know what it did with each pin.
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Change subject: cpu/x86/smm_module_load: Rewrite setup_stub
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/63478/comment/2e06ae0e_26e90e6e
PS4, Line 323: smm_stub_place_staggered_entry_points
> > the bug was filling in the stub_params->c_handler before calling this function correct? […]
sorry I missed the word "not" in there, "not filling it before calling" 😊
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Change subject: cpu/x86/smm: Refactor creating a stub/save state map
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63474/comment/4e91fd67_75818512
PS2, Line 9: This code was very hard to read so rewrite in a mostly pure functional
: way.
fix English!
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Change subject: cpu/x86/smm_module_load: Rewrite setup_stub
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/63478/comment/d58e8f3e_8133a179
PS4, Line 323: smm_stub_place_staggered_entry_points
> the bug was filling in the stub_params->c_handler before calling this function correct?
the bug is filling it after actually.
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Change subject: tpm: Refactor TPM Kconfig dimensions
......................................................................
Patch Set 6:
(12 comments)
Patchset:
PS6:
Thanks Jes, this looks great!
File src/drivers/i2c/tpm/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/63424/comment/9224ce55_1a6b8ebe
PS6, Line 3: ifeq ($(CONFIG_I2C_TPM),y)
Might as well wrap all lines in the file in this?
In fact, I think it would be good to wrap all this in both
ifeq ($(CONFIG_TPM)$(CONFIG_I2C_TPM),yy)
and do the same for the SPI, CRB and LPC drivers. CONFIG_TPM being off should ensure that none of this code ever runs, but right now there's not really much static checking for that. If we avoid even compiling it we both save build time and make it easier to see if someone accidentally calls TPM functions in the wrong config.
File src/drivers/tpm/Makefile.inc:
PS6:
This whole Makefile should also be wrapped in a CONFIG_TPM check.
File src/mainboard/google/herobrine/Kconfig:
https://review.coreboot.org/c/coreboot/+/63424/comment/9c62ff21_e5d514a0
PS6, Line 28: select TPM_GOOGLE_CR50
This needs an `if !BOARD_GOOGLE_SENOR`
File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/63424/comment/44304c26_521388e2
PS6, Line 87: if (!CONFIG(SPI_TPM)) {
This doesn't seem to make a difference for the currently available configurations, but I think it would be cleaner to also check && !CR50 here.
File src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c:
https://review.coreboot.org/c/coreboot/+/63424/comment/5c4ea59b_3f6e4f08
PS6, Line 594: /* CLK_25M_MEMORY_MAPPED_TPM_CPU */
You probably don't want to replace this.
File src/security/tpm/tss/vendor/cr50/Kconfig:
https://review.coreboot.org/c/coreboot/+/63424/comment/79a6510c_949d3879
PS6, Line 10: depends on TPM2
These shouldn't actually depend on TPM2 now, and neither should TPM_GOOGLE. The goal is that even if the mainboard has a Cr50/Ti50 TPM, the user can still disable it by selecting NO_TPM in menuconfig.
https://review.coreboot.org/c/coreboot/+/63424/comment/231f26f6_6586c305
PS6, Line 12: default n
nit: you don't need to specify `default n`, but if you do it's customary to put it above the `select`s.
https://review.coreboot.org/c/coreboot/+/63424/comment/a1b02d52_6b76c65a
PS6, Line 20: OOGLE_CR50 || TPM_GOOGLE_TI50
Just TPM_GOOGLE?
File src/soc/intel/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/63424/comment/30ac40ed_aa3d157a
PS6, Line 23: all-$(CONFIG_TPM_GOOGLE) += tpm_tis.c
nit: a bit off-topic, but does Ti50 actually still require waiting for the sideband interrupt before doing the next transaction? I was hoping we would have gotten rid of that requirement now... (because that's what this code here is for)
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/63424/comment/426cd070_74804dfb
PS6, Line 25: config TPM_GOOGLE_IMMEDIATELY_COMMIT_FW_SECDATA
Also a bit off-topic but it would probably be good to move this to tss/vendor/google. It shouldn't really depend on CHROMEOS.
File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/63424/comment/3d623ed1_8869ecc0
PS6, Line 19: if (CONFIG(SPI_TPM) && CONFIG(TPM_GOOGLE_CR50)) {
Is there a reason to specifically check SPI_TPM here? Looks to me like the important factor here was just Cr50, but the only boards affected by this all used SPI.
We should probably also check if the TPM is enabled here, which should always have been done but is an edge case people tend to forget. So check (CONFIG(TPM2) && CONFIG(TPM_GOOGLE_CR50))?
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Change subject: cpu/x86/smm_module_load: Rewrite setup_stub
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/63478/comment/9c7242d0_17bf0869
PS4, Line 323: smm_stub_place_staggered_entry_points
the bug was filling in the stub_params->c_handler before calling this function correct?
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Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 )
Change subject: soc/intel/common: implement ioc driver
......................................................................
Patch Set 8:
(9 comments)
File src/soc/intel/common/block/include/intelblocks/ioc.h:
https://review.coreboot.org/c/coreboot/+/63198/comment/26380ed0_26c8ea52
PS5, Line 10: <soc/ioc_reg.h>
> I'll remove this option for now. […]
Ack
https://review.coreboot.org/c/coreboot/+/63198/comment/5645d3b0_7c3be2a7
PS5, Line 12: /*
> nit: Add space after comment beginning
Ack
https://review.coreboot.org/c/coreboot/+/63198/comment/e2fa77bb_ed06dc2e
PS5, Line 15:
: void ioc_reg_write32(uint32_t offset, uint32_t value);
: uint32_t ioc_reg_read32(uint32_t offset);
> outside gpmr. […]
updated code to use gpmr api in other drivers and ioc api will be used in gpmr driver.
File src/soc/intel/common/block/include/intelblocks/ioc_reg.h:
https://review.coreboot.org/c/coreboot/+/63198/comment/58a28d0c_d11424a4
PS5, Line 7: A
> Please use lowercase for hex
Ack
https://review.coreboot.org/c/coreboot/+/63198/comment/e3668c36_6d490cfb
PS5, Line 8: C
> Ditto
Ack
https://review.coreboot.org/c/coreboot/+/63198/comment/6eb03c72_e0eab27d
PS5, Line 13: FFE
> Ditto
Ack
https://review.coreboot.org/c/coreboot/+/63198/comment/4bdd5d89_be8f12d7
PS5, Line 14: A7C
> Ditto
Ack
https://review.coreboot.org/c/coreboot/+/63198/comment/2b27313a_f4f38351
PS5, Line 15: A
> Ditto
Ack
File src/soc/intel/common/block/ioc/Kconfig:
https://review.coreboot.org/c/coreboot/+/63198/comment/9a581d32_2a149e85
PS5, Line 1: SOC_INTEL_COMMON_BLOCK_IOC
> you are depending on MCH_BASE_ADDRESS being programmed for IOC read/write, hence, required driver is […]
Do we have KConfig for this?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982
Gerrit-Change-Number: 63198
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