coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu/x86/smm_module_loader: Add a convenient ss_top
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63477 ) Change subject: cpu/x86/smm_module_loader: Add a convenient ss_top ...................................................................... Patch Set 3: Verified+1 (1 comment) File src/cpu/x86/smm/smm_module_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145822): https://review.coreboot.org/c/coreboot/+/63477/comment/fa461db5_9046ef34 PS3, Line 128: printk(BIOS_DEBUG, " Save state [0x%lx-0x%lx[\n", cpus[i].ss_start, cpus[i].ss_top); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7 Gerrit-Change-Number: 63477 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:57:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Drop 'entry' struct element
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63476 ) Change subject: cpu/x86/smm: Drop 'entry' struct element ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e8905e3ed940fb34280c939d6f2f1fce8480a7 Gerrit-Change-Number: 63476 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:54:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Julius Werner (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 8: (3 comments) File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/63251/comment/efbeb354_6caf97e7 PS8, Line 91: struct cb_pcie pcie_info; Copying whole coreboot table entries in here isn't great (I guess we were lazy for the framebuffer because it's so big), it wastes space for `tag` and `size` entries that are no longer relevant here. You should define individual fields instead. File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/4a153ce7_a0422a86 PS8, Line 176: uint64_t atu_base; /* Base address of Address translation unit */ You should really use struct lb_uint64 for all of these to avoid unintentional padding differences between architectures. Some of the existing records already do that wrong (and should probably be fixed) but they happen to get lucky with the alignment. You don't. (The whole struct lb_uint64 mechanism is really ugly to work with, of course. I think the problem could be solved in a much cleaner way with something like `typedef __aligned(4) uint64_t lb_uint64_t;`, if someone was willing to spend the time to convert it all.) File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/63251/comment/6123ea77_fb0612f7 PS8, Line 136: lb_pcie->config_size = pcie->config_size; Sorry, but something looks off here. You're just shuffling everything from the `pcie` argument into the coreboot table here, but in CB:63252 `pcie` is a stack allocation with only one initialized field. All those other fields would be leaking random stack garbage into the coreboot table. If you don't need those fields on that platform, they should be deterministically zeroed. The whole call order here seems a bit weird, I'd try to follow the lb_gpios() model instead. So write_coreboot_table() would call void lb_pcie(struct lb_header *header) { struct lb_pcie pcie = { .tag = LB_TAG_PCIE, .size = sizeof(pcie) }; if (fill_lb_pcie(&pcie) != CB_SUCCESS) return; memcpy(lb_new_record(header), &pcie, sizeof(pcie)); } and then the platform can choose to implement fill_lb_pcie() to fill out the structure, or otherwise a default weak implementation would return CB_ERR. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 8 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:46:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_loader.c: Rewrite setup more purely function
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Edward O'Callaghan. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63475 ) Change subject: cpu/x86/smm_module_loader.c: Rewrite setup more purely function ...................................................................... Patch Set 3: (8 comments) File src/cpu/x86/smm/smm_module_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/46e14af3_17f1c428 PS3, Line 468: const uintptr_t handler_base = ALIGN_DOWN(fx_save_area_base - handler_size, handler_alignment); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/235dd440_2c554d82 PS3, Line 469: printk(BIOS_DEBUG, "smihandler [0x%lx-0x%lx[\n", handler_base, handler_base + handler_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/1babc606_e66bd5ee PS3, Line 515: return smm_module_setup_stub(stub_segment_base, smram_size, params, (void *)fx_save_area_base); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/d7ec5634_e6dd9409 PS3, Line 561: const uintptr_t save_state_bottom = cpus[params->num_concurrent_save_states - 1].ss_start; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/c4811d73_ff907311 PS3, Line 569: printk(BIOS_ERR, "fxsave wont fit in smram\n"); 'wont' may be misspelled - perhaps 'won't'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/004b18bb_013fda90 PS3, Line 574: const size_t bottom_space = cpus[params->num_concurrent_save_states - 1].code_start - smm_stack_top; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/9c559de3_9e78919e PS3, Line 583: printk(BIOS_ERR, "handler wont fit in top of smram\n"); 'wont' may be misspelled - perhaps 'won't'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145820): https://review.coreboot.org/c/coreboot/+/63475/comment/fafda1b6_2575ab8b PS3, Line 590: printk(BIOS_ERR, "handler wont fit in bottom of smram\n"); 'wont' may be misspelled - perhaps 'won't'? -- To view, visit https://review.coreboot.org/c/coreboot/+/63475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Gerrit-Change-Number: 63475 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:46:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Refactor creating a stub/save state map
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63474 ) Change subject: cpu/x86/smm: Refactor creating a stub/save state map ...................................................................... Patch Set 2: (2 comments) File src/cpu/x86/smm/smm_module_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145819): https://review.coreboot.org/c/coreboot/+/63474/comment/8f4e9291_e5fd104b PS2, Line 106: const size_t cpus_per_segment = (SMM_CODE_SEGMENT_SIZE - SMM_ENTRY_OFFSET) / needed_ss_size; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145819): https://review.coreboot.org/c/coreboot/+/63474/comment/88d33132_1e7e70ad PS2, Line 127: printk(BIOS_DEBUG, " Stub [0x%lx-0x%lx[\n", cpus[i].code_start, cpus[i].code_end); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Gerrit-Change-Number: 63474 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:45:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61494 ) Change subject: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG ...................................................................... Patch Set 6: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Gerrit-Change-Number: 61494 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:34:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61494 ) Change subject: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG ...................................................................... Patch Set 5: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Gerrit-Change-Number: 61494 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:33:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Allow up to 255 cores
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63483 ) Change subject: cpu/qemu-x86: Allow up to 255 cores ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eea91fb09f47de8b06de9fa7eb2ad66ef4dc7e2 Gerrit-Change-Number: 63483 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:33:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/smbios.c: Fix for CONFIG_MAX_CPUS > 255
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63482 ) Change subject: arch/x86/smbios.c: Fix for CONFIG_MAX_CPUS > 255 ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I079c99006fea95ba3dc2fb02c95a3747af55e218 Gerrit-Change-Number: 63482 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:29:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_loader: Update logging
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63481 ) Change subject: cpu/x86/smm_module_loader: Update logging ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84d49a394cc53d78f1e1d3936502ac16810daf9f Gerrit-Change-Number: 63481 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:28:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022