coreboot-gerrit April 2022

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Change in coreboot[master]: cpu/x86/smm_module_loader: Drop superfluous check
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63480 to look at the new patch set (#4). Change subject: cpu/x86/smm_module_loader: Drop superfluous check ...................................................................... cpu/x86/smm_module_loader: Drop superfluous check Checking if the stack encroaches on the entry points is done in other parts of the code. Change-Id: I275d5dda9c69cc89608450ae27dd5dbd581e3595 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 3 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/63480/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I275d5dda9c69cc89608450ae27dd5dbd581e3595 Gerrit-Change-Number: 63480 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm_module_loader.c: Rewrite setup more purely function
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63475 to look at the new patch set (#3). Change subject: cpu/x86/smm_module_loader.c: Rewrite setup more purely function ...................................................................... cpu/x86/smm_module_loader.c: Rewrite setup more purely function It's much easier to read code if you don't need to keep track of the state of a function, so rewrite it in mostly pure functional code. Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 117 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63475/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Gerrit-Change-Number: 63475 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Refactor creating a stub/save state map
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63474 to look at the new patch set (#2). Change subject: cpu/x86/smm: Refactor creating a stub/save state map ...................................................................... cpu/x86/smm: Refactor creating a stub/save state map This code was very hard to read so rewrite in a mostly pure functional way. Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 28 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63474/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Gerrit-Change-Number: 63474 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taniks: Enable Genesys L1 max entry delay
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63131 ) Change subject: mb/google/brya/var/taniks: Enable Genesys L1 max entry delay ...................................................................... mb/google/brya/var/taniks: Enable Genesys L1 max entry delay The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 79320fd..614fdc3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -155,6 +155,7 @@ select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX config BOARD_GOOGLE_VELL bool "-> Vell" -- To view, visit https://review.coreboot.org/c/coreboot/+/63131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Gerrit-Change-Number: 63131 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63169 ) Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... soc/intel/common: Update CSE sub partition update The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Also, did boot test on Kano system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63169 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 33 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 2756814..ca6d7d3 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -127,6 +127,7 @@ struct cse_bp_info bp_info; } __packed; +static const char * const cse_regions[] = {"RO", "RW"}; bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { @@ -779,16 +780,43 @@ } } -static bool cse_sub_part_get_target_rdev(struct region_device *target_rdev, - const char *region_name, enum bpdt_entry_type type) +static bool cse_locate_area_as_rdev_rw(const struct cse_bp_info *cse_bp_info, + size_t bp, struct region_device *cse_rdev) +{ + struct region_device cse_region_rdev; + uint32_t size; + uint32_t start_offset; + uint32_t end_offset; + + if (!cse_get_rw_rdev(&cse_region_rdev)) + return false; + + if (!strcmp(cse_regions[bp], "RO")) + cse_get_bp_entry_range(cse_bp_info, RO, &start_offset, &end_offset); + else + cse_get_bp_entry_range(cse_bp_info, RW, &start_offset, &end_offset); + + size = end_offset + 1 - start_offset; + + if (rdev_chain(cse_rdev, &cse_region_rdev, start_offset, size)) + return false; + + printk(BIOS_DEBUG, "cse_lite: CSE %s partition: offset = 0x%x, size = 0x%x\n", + cse_regions[bp], start_offset, size); + return true; +} + +static bool cse_sub_part_get_target_rdev(const struct cse_bp_info *cse_bp_info, + struct region_device *target_rdev, size_t bp, enum bpdt_entry_type type) { struct bpdt_header bpdt_hdr; struct region_device cse_rdev; struct bpdt_entry bpdt_entries[MAX_SUBPARTS]; uint8_t i; - if (fmap_locate_area_as_rdev_rw(region_name, &cse_rdev) < 0) { - printk(BIOS_ERR, "cse_lite: Failed to locate %s in the FMAP\n", region_name); + if (!cse_locate_area_as_rdev_rw(cse_bp_info, bp, &cse_rdev)) { + printk(BIOS_ERR, "cse_lite: Failed to locate %s in the CSE Region\n", + cse_regions[bp]); return false; } @@ -925,7 +953,6 @@ struct fw_version target_fw_ver, source_fw_ver; enum csme_failure_reason rv; size_t size; - static const char * const cse_regions[] = {"CSE_RO", "CSE_RW"}; void *subpart_cbfs_rw = cbfs_map(name, &size); if (!subpart_cbfs_rw) { @@ -941,7 +968,7 @@ /* Trigger sub-partition update in CSE RO and CSE RW */ for (size_t bp = 0; bp < ARRAY_SIZE(cse_regions); bp++) { - if (!cse_sub_part_get_target_rdev(&target_rdev, cse_regions[bp], type)) { + if (!cse_sub_part_get_target_rdev(cse_bp_info, &target_rdev, bp, type)) { rv = CSE_LITE_SKU_SUB_PART_ACCESS_ERR; goto error_exit; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/tables.c: Increase MAX_SMBIOS_SIZE
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63484 ) Change subject: arch/x86/tables.c: Increase MAX_SMBIOS_SIZE ...................................................................... arch/x86/tables.c: Increase MAX_SMBIOS_SIZE Systems have a lot more cores now and 4KiB is not cutting it. E.g. for a system with 255 cores more than 16KiB is needed. We could also make this a Kconfig parameter but it's probably not worth having such micro optimizations to save a few KiB. Change-Id: Idd47e55d8d679cc70eae996ee1af3ad7eaa1d0cc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/tables.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63484/1 diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 1018dce..8d2f7b6 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -142,7 +142,7 @@ { unsigned long high_table_pointer; -#define MAX_SMBIOS_SIZE (4 * KiB) +#define MAX_SMBIOS_SIZE (32 * KiB) high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); -- To view, visit https://review.coreboot.org/c/coreboot/+/63484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd47e55d8d679cc70eae996ee1af3ad7eaa1d0cc Gerrit-Change-Number: 63484 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: lower maintenance level of super I/O and superiotool
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63417 ) Change subject: MAINTAINERS: lower maintenance level of super I/O and superiotool ...................................................................... MAINTAINERS: lower maintenance level of super I/O and superiotool I don't really get around to review super I/O or superiotool patches any more, so lower the maintenance level of those. If anyone else wants to step up as new maintainer for those two, feel free to do so. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63417 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M MAINTAINERS 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 930d37e..3181ef3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -880,7 +880,7 @@ SUPERIOS & SUPERIOTOOL M: Felix Held <felix-coreboot(a)felixheld.de> -S: Maintained +S: Odd Fixes F: src/superio/ F: util/superiotool/ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c Gerrit-Change-Number: 63417 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ChromeOS: Add DECLARE_x_CROS_GPIOS()
by Kyösti Mälkki (Code Review) 07 Apr '22

07 Apr '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58899 ) Change subject: ChromeOS: Add DECLARE_x_CROS_GPIOS() ...................................................................... ChromeOS: Add DECLARE_x_CROS_GPIOS() Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/amd/chausie/chromeos.c M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/skyrim/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/adlrvp/gpio_n.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h 55 files changed, 73 insertions(+), 290 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/chromeos.c b/src/mainboard/amd/chausie/chromeos.c index fffde8d..fc7cf5d 100644 --- a/src/mainboard/amd/chausie/chromeos.c +++ b/src/mainboard/amd/chausie/chromeos.c @@ -18,9 +18,4 @@ return 0; } -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - /* No ChromeOS GPIOs */ - *num = 0; - return NULL; -} +DECLARE_NO_CROS_GPIOS(); diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index acef8d1..72a5b3d 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -18,9 +18,4 @@ return 0; } -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - /* No ChromeOS GPIOs */ - *num = 0; - return NULL; -} +DECLARE_NO_CROS_GPIOS(); diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 7fd2add..0f29c84 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -19,12 +19,8 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"), }; +DECLARE_CROS_GPIOS(cros_gpios); -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 71f5099..84940e2 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -35,12 +35,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index df051a8..227e595 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -69,12 +69,7 @@ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index c540d76..93f5393 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -426,11 +426,7 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) { diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index da0048a..fb7bc21 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -445,11 +445,7 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) { diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index 29698bc..06fc1b7 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -432,12 +432,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) { diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index f31967c..4dcf14f 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -52,12 +52,7 @@ CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 6ecab94..5c23230 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -59,12 +59,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index e1b920a..7a403b5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -474,8 +474,4 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 9f77028..eb9b72d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -407,11 +407,7 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); /* Weak implementation of overrides */ const struct pad_config *__weak variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 4a33faa..6220bf2 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -254,11 +254,7 @@ CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); void variant_mainboard_post_init_params(FSPM_UPD *mupd) { diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index fadec40..81fc391 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -31,12 +31,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index 4787d2d..0f52fe3 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -264,8 +264,4 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index c90d12d..299a372 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -30,12 +30,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index c5530db..cbffcf8 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -22,12 +22,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f9ffcd9..eab831a 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -418,11 +418,7 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); /* Weak implementation of overrides */ const struct pad_config *__weak override_gpio_table(size_t *num) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index c5ebc72..d8ecb4e 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -71,12 +71,7 @@ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index c7f7671..4b71175 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -29,12 +29,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index a1ac2d6..8c6749b 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -36,12 +36,7 @@ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 61e8e0d..76f74a5 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -382,8 +382,4 @@ CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index dc476f9..10314f5 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -50,12 +50,7 @@ CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index ea9de7a..c7abe77 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -388,11 +388,7 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); const struct pad_config * __weak variant_romstage_gpio_table(size_t *num) { diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index eae2357..a225821 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -42,12 +42,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 8263459..aeb8edf 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -398,8 +398,4 @@ CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME), }; -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index b60e031..1a814aa 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -409,8 +409,4 @@ CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME), }; -const struct cros_gpio * variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index e91415b..fbaeb39 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -259,8 +259,4 @@ CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 7aaffdf..7f226e4 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -247,8 +247,4 @@ CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c index 347e9d0..c749b4f 100644 --- a/src/mainboard/google/skyrim/chromeos.c +++ b/src/mainboard/google/skyrim/chromeos.c @@ -19,9 +19,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 9e0ab0c..ddc6e3a 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -27,12 +27,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 2f3ae8c..8abdb67 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -79,8 +79,4 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 05c757c..8d9dd6d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -467,8 +467,4 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index a975099..8c579c3 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -28,12 +28,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index d553180..92a8c30 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -279,9 +279,4 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 33b5a1d..5d23668 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -190,9 +190,4 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c index 364deac..b985d53 100644 --- a/src/mainboard/intel/adlrvp/gpio_n.c +++ b/src/mainboard/intel/adlrvp/gpio_n.c @@ -236,9 +236,4 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 05280b15..e82edeb 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -47,8 +47,4 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 9e5f243..1be950c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -609,8 +609,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 621ecfd..727258e 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -44,8 +44,4 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 0b2c680..6ef1eac 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -263,8 +263,4 @@ static const struct cros_gpio cros_gpios[] = { }; -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index 94a6a79..160f0d3 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -109,8 +109,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index 94a6a79..160f0d3 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -109,8 +109,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 27395db..eab0fe5 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -351,8 +351,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index f64f5bd..f1c02ea 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -59,12 +59,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 2bb59fb..b285dde 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -30,12 +30,7 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); int get_ec_is_trusted(void) { diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c index f416e09..9090774 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c @@ -349,8 +349,4 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index a6a0af2..0cd2be4 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -38,8 +38,4 @@ CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index b9fdac8..2a1eb3f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -136,8 +136,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 1c007d7..eb0176f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -132,8 +132,4 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 49da437..89a14da 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -36,8 +36,4 @@ CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index e5c8d30..ba5eabe 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -90,8 +90,4 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 95801c1..61782f8 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -83,8 +83,4 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 383cd31..801f33d 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -12,7 +12,8 @@ size_t i, num; int gpio_num; - gpios = variant_cros_gpios(&num); + num = variant_cros_gpio.count; + gpios = variant_cros_gpio.gpios; if (!gpios) return; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 2ab51be..cd3b603 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -98,6 +98,23 @@ #define CROS_GPIO_PE_AH(num, dev) \ CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) -const struct cros_gpio *variant_cros_gpios(size_t *num); +struct cros_gpio_pack { + int count; + const struct cros_gpio *gpios; +}; + +extern const struct cros_gpio_pack variant_cros_gpio; + +#define DECLARE_NO_CROS_GPIOS() \ + const struct cros_gpio_pack variant_cros_gpio = \ + { .count = 0, .gpios = NULL } + +#define DECLARE_CROS_GPIOS(x) \ + const struct cros_gpio_pack variant_cros_gpio = \ + { .count = ARRAY_SIZE(x), .gpios = x } + +#define DECLARE_WEAK_CROS_GPIOS(x) \ + const struct cros_gpio_pack __weak variant_cros_gpio = \ + { .count = ARRAY_SIZE(x), .gpios = x } #endif /* __CHROMEOS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Gerrit-Change-Number: 58899 Gerrit-PatchSet: 19 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61494 ) Change subject: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG ...................................................................... Patch Set 5: Code-Review-1 (1 comment) Patchset: PS5: Does not look that clean. Probably copy pasta of headers. -- To view, visit https://review.coreboot.org/c/coreboot/+/61494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Gerrit-Change-Number: 61494 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:34:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_loader: Add a convenient ss_top
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63477 ) Change subject: cpu/x86/smm_module_loader: Add a convenient ss_top ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/smm/smm_module_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145794): https://review.coreboot.org/c/coreboot/+/63477/comment/83b7c94e_3d7d2cbe PS1, Line 128: printk(BIOS_DEBUG, " Save state [0x%lx-0x%lx[\n", cpus[i].ss_start, cpus[i].ss_top); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7 Gerrit-Change-Number: 63477 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:33:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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